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Integrated circuit package bond pad having plurality of conductive members 원문보기

IPC분류정보
국가/구분 United States(US) Patent 등록
국제특허분류(IPC7판)
  • H01L-023/48
  • H01L-023/485
  • H01L-029/40
출원번호 US-0680664 (2003-10-07)
등록번호 US-7372153 (2008-05-13)
발명자 / 주소
  • Kuo,Yian Liang
  • Lin,Yu Chang
출원인 / 주소
  • Taiwan Semiconductor Manufacturing Co., Ltd
대리인 / 주소
    Haynes Boone, LLP
인용정보 피인용 횟수 : 11  인용 특허 : 35

초록

An integrated circuit package bond pad includes an insulating layer and an electrode located over the insulating layer. The electrode has a first surface configured to be bonded to external circuitry and a second surface opposite the first surface. A plurality of conductive members is located in the

대표청구항

The invention claimed is: 1. An integrated circuit package bond pad, comprising: an insulating layer; an electrode located over the insulating layer and having a plurality of discrete conductors separated by portions of a dielectric layer, wherein each of the plurality of discrete conductors has a

이 특허에 인용된 특허 (35)

  1. Chittipeddi Sailesh ; Ryan Vivian, Bond pad design for integrated circuits.
  2. Shiue Ruey-Yun,TWX ; Wu Wen-Teng,TWX ; Shieh Pi-Chen,TWX ; Liu Chin-Kai,TWX, Bond pad structure for the via plug process.
  3. Lin Shi-Tron,TWX, Bond pad with pad edge strengthening structure.
  4. Edgar R. Zuniga ; Samuel A. Ciani, Bonding over integrated circuits.
  5. Wang, Kun-Chih, Bonding pad structure.
  6. Wu Jyh-Ren,TWX ; Liu Chia-Chen,TWX, Bonding pad structure and manufacturing method thereof.
  7. Huang Yung-Sheng,TWX ; Lin Chiu-Ching,TWX ; Lu Chun-Hung,TWX ; Hwang Ruey-Lian,TWX, Bonding pad structure to prevent inter-metal dielectric cracking and to improve bondability.
  8. Chan Chin-Jong,TWX ; Lin Shi-Tron,TWX, Bone-pad with pad edge strengthening structure.
  9. Axel Christoph Brintzinger, Chip crack stop design for semiconductor chips.
  10. Lee Shaw Wei ; Takiar Hem P. ; Mathew Ranjan J., Chip scale package and method for manufacture thereof.
  11. Chung, Chee-Yee; Figueroa, David G.; Sankman, Robert L., Electrical assembly with vertical multiple layer structure.
  12. Kida Tsuyoshi,JPX ; Oyachi Kenji,JPX, Electrode structure of semiconductor element.
  13. Mukul Saran ; Charles A. Martin ; Ronald H. Cox, Fine pitch system and method for reinforcing bond pads in semiconductor devices.
  14. Lee, Soo-cheol; Ahn, Jong-hyon; Son, Kyoung-mok; Shin, Heon-jong; Lee, Hyae-ryoung; Kim, Young-pill; Jung, Moo-jin; Wang, Son-jong; Yoo, Jae-Cheol, Integrated circuit bonding pads including conductive layers with arrays of unaligned spaced apart insulating islands therein and methods of forming same.
  15. Lee Soo-cheol,KRX ; Ahn Jong-hyon,KRX ; Lee Hyae-ryoung,KRX, Integrated circuit bonding pads including intermediate closed conductive layers having spaced apart insulating islands therein.
  16. Glenn Thomas P. ; Hollaway Roy D.,PHX ; Panczak Anthony E., Integrated circuit package having adhesive bead supporting planar lid above planar substrate.
  17. Seyyedy,Mirmajid; Hush,Glen E.; Tuttle,Mark E.; Vollman,Terry C., Integrated circuits with contemporaneously formed array electrodes and logic interconnects.
  18. Yu, Chen-Hua; Liu, Chung-Shi, Metal bond pad for low-k inter metal dielectric.
  19. John J. Ellis-Monaghan ; Paul M. Feeney ; Robert M. Geffken ; Howard S. Landis ; Rosemary A. Previti-Kelly ; Bette L. Bergman Reuter ; Matthew J. Rutten ; Anthony K. Stamper ; Sally J. Yankee, Method and structure of column interconnect.
  20. Batra, Shubneesh; Chaine, Michael D.; Keeth, Brent; Akram, Salman; Manning, Troy A.; Johnson, Brian; Martin, Chris G.; Merritt, Todd A.; Smith, Eric J., Method and structures for reduced parasitic capacitance in integrated circuit metallizations.
  21. Yiu Ho-Yin,TWX ; Wu Lin-June,TWX ; Chen Bor-Cheng,TWX ; Horng J. H.,TWX, Method for fabricating a stress buffered bond pad.
  22. Pozder, Scott K.; Kobayashi, Thomas S., Method for forming a semiconductor device having a mechanically robust pad interface.
  23. Kobayashi, Thomas S.; Pozder, Scott K., Method of forming a bond pad and structure thereof.
  24. Chen,Sheng Hsiung, Method of improving copper pad adhesion.
  25. Cheng Chung Lin TW; Chen Hua Yu TW; Tsu Shih TW; Weng Chang TW, Method of reducing dishing and erosion using a sacrificial layer.
  26. Soo-cheol Lee KR; Jong-hyon Ahn KR; Hyae-ryoung Lee KR, Methods of fabricating integrated circuit bonding pads including intermediate closed conductive layers having spaced apart insulating islands therein.
  27. Bachman, Mark Adam; Chesire, Daniel Patrick; Merchant, Sailesh Mansinh; Osenbach, John William; Steiner, Kurt George, Reinforced bond pad.
  28. Tanaka, Kazuo, Semiconductor device and a method for making the same that provide arrangement of a connecting region for an external connecting terminal.
  29. Nozaki Masahiko (Hyogo JPX), Semiconductor device structure including multiple interconnection layers with interlayer insulating films.
  30. Yutaka Aoki JP; Hiroshi Takenaka JP; Ichiro Mihara JP, Semiconductor device which prevents leakage of noise generated in a circuit element forming area and which shields against external electromagnetic noise.
  31. Sano, Fumihiko, Semiconductor integrated circuit device and method of manufacturing the same.
  32. Yiu Ho-Yin,HKX ; Wu Lin-June,TWX ; Chen Bor-Cheng,TWX ; Horng Jan-Her,TWX, Stress buffered bond pad and method of making.
  33. Moslehi Mehrdad M., Ultra high-speed chip interconnect using free-space dielectrics.
  34. Chung, Chee-Yee; Figueroa, David G.; Sankman, Robert L., Vertical electronic circuit package.
  35. Secker, David A.; Jain, Nirmal, Wirebond assembly for high-speed integrated circuits.

이 특허를 인용한 특허 (11)

  1. Lee, Jin-Yuan; Chen, Ying-Chih; Lin, Mou-Shiung, Method of wire bonding over active area of a semiconductor circuit.
  2. Lee, Jin-Yuan; Chen, Ying-Chih; Lin, Mou-Shiung, Method of wire bonding over active area of a semiconductor circuit.
  3. Lee, Jin-Yuan; Chen, Ying-Chih; Lin, Mou-Shiung, Method of wire bonding over active area of a semiconductor circuit.
  4. Lee, Jin-Yuan; Chen, Ying-Chih; Lin, Mou-Shiung, Method of wire bonding over active area of a semiconductor circuit.
  5. Lee, Jin-Yuan; Chen, Ying-Chih; Lin, Mou-Shiung, Method of wire bonding over active area of a semiconductor circuit.
  6. Lee, Jin-Yuan; Chen, Ying-chih, Method of wire bonding over active area of a semiconductor circuit.
  7. Olson, Scott Eugene, Semiconductor laser with cathode metal layer disposed in trench region.
  8. Olson, Scott Eugene, Semiconductor laser with cathode metal layer disposed in trench region.
  9. Olson, Scott, Semiconductor laser with test pads.
  10. Chen, Hsien-Wei; Chen, Ying-Ju; Liu, Yu-Wen; Tsai, Hao-Yi; Jeng, Shin-Puu, Semiconductor test pad structures.
  11. Chen, Hsien-Wei; Chen, Ying-Ju; Liu, Yu-Wen; Tsai, Hao-Yi; Jeng, Shin-Puu, Semiconductor test pad structures.
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