초록 ▼

A programmable circuit receives configuration data from an external source, stores the firmware in a memory, and then downloads the firmware from the memory. Such a programmable circuit allows a system, such as a computing machine, to modify the programmable circuit's configuration, thus eliminating

A programmable circuit receives configuration data from an external source, stores the firmware in a memory, and then downloads the firmware from the memory. Such a programmable circuit allows a system, such as a computing machine, to modify the programmable circuit's configuration, thus eliminating the need for manually reprogramming the configuration memory. For example, if the programmable circuit is an FPGA that is part of a pipeline accelerator, a processor coupled to the accelerator can modify the configuration of the FPGA. More specifically, the processor retrieves from a configuration registry firmware that represents the modified configuration, and sends the firmware to the FPGA, which then stores the firmware in a memory such as an electrically erasable and programmable read-only memory (EEPROM). Next, the FPGA downloads the firmware from the memory into its configuration registers, and thus reconfigures itself to have the modified configuration.

대표청구항 ▼

What is claimed is: 1. A programmable logic integrated circuit operable to function as an end point on an industry standard bus, the programmable logic integrated circuit including an interface to the industry standard bus and being operable through the interface to, receive multiple versions of fi

What is claimed is: 1. A programmable logic integrated circuit operable to function as an end point on an industry standard bus, the programmable logic integrated circuit including an interface to the industry standard bus and being operable through the interface to, receive multiple versions of firmware from an external source, each version of firmware representing a corresponding operating configuration; store the multiple versions of firmware in a memory; download a selected one of the versions of firmware from the memory; and configure itself using the downloaded firmware to operate in the corresponding operating configuration; wherein the programmable logic integrated circuit further comprises: at least one hardwired pipeline, each hardwired pipeline operable to process respective data without executing program instructions; a communication shell coupled to the hardwired pipelines and operable to transfer data to and from the hardwired pipelines; and a communication interface coupled to the interface to the industry standard bus, the communication interface operable to communicate with the interface to the industry standard bus to transfer data to and from the programmable logic integrated circuit over the industry standard bus, and the communication interface further operable to transfer data to and from each hardwired pipeline via the communication shell. 2. The programmable circuit of claim 1 wherein the memory comprises a nonvolatile memory. 3. The programmable circuit of claim 1 wherein the memory comprises memory external to the programmable logic integrated circuit. 4. A programmable logic integrated circuit operable to function as an end point on an industry standard bus, the programmable logic integrated circuit including an interface to the industry standard bus and being operable to, download from a memory storing a plurality of versions of firmware a first firmware version that represents a first configuration; configure itself using the first firmware version; operate in the first configuration; download from the memory a second firmware version that represents a second configuration; configure itself using the second firmware version; and operate in the second configuration; wherein the programmable logic integrated circuit is further operable to: receive the second firmware version from an external source via the industry standard bus and interface to the industry standard bus while operating in the first configuration; and storing the second firmware version in the memory while operating in the first configuration, and wherein the second firmware version may only be received when operating in the first configuration. 5. The programmable logic integrated circuit of claim 4 wherein the memory comprises an electrically erasable and programmable read-only memory. 6. The programmable logic integrated circuit of claim 4 wherein the circuit comprises a field-programmable gate array. 7. A programmable-circuit unit, comprising: A pipeline bus operable to communicate data through an industry standard bus protocol; a memory operable to store a plurality of versions of firmware data, each version respectively representing a corresponding configuration of the programmable-circuit unit; and a programmable logic integrated circuit coupled to the memory and operable to function as an end point on the pipeline bus, the programmable logic integrated circuit including an interface to the pipeline bus and being operable to, download a first selected one of the versions of firmware data from the memory operate in the configuration corresponding to the first selected version of firmware data, download a second selected one of the versions of firmware data from the memory, and operate in the configuration corresponding to the second selected version of firmware data; wherein the programmable logic integrated circuit is further operable to: receive the second selected version of firmware data from an external source via the pipeline bus and the interface to the pipeline bus while operating in the first configuration; and store the second selected version of firmware data in the memory while operating in the first configuration, and wherein the second selected firmware version of firmware may only be received and stored when operating in the configuration corresponding to the first selected version of firmware data. 8. The programmable-circuit unit of claim 7 wherein the programmable logic integrated circuit is operable to load the second firmware while operating in the first configuration. 9. The programmable-circuit unit of claim 7 further comprising a router coupled to the pipeline bus. 10. A programmable-circuit unit, comprising: a memory operable to store a plurality of firmware configurations, each firmware configuration respectively representing a corresponding operational configuration; a first programmable logic integrated circuit coupled to the memory and including an interface to an industry standard bus, the first programmable logic integrated circuit operable to receive the firmware configurations via the industry standard bus and to store these configurations in the memory, and wherein the first programmable logic integrated circuit is further operable to, download a first selected one of the firmware configurations from the memory, operate in the operational configuration corresponding to the first selected firmware configuration, download a first different one of the firmware configurations from the memory, and operate in the operational configuration corresponding to the first different firmware configuration; and a second programmable logic integrated circuit coupled to the memory and to the first programmable circuit and including an interface that is operable to, download a second selected one of the firmware configurations from the memory, operate in the operational configuration corresponding to the second selected one of the firmware configurations, download a second different one of the firmware configurations from the memory, and operate in the operational configuration corresponding to the second different firmware configuration; and wherein the second programmable logic integrated circuit further comprises: at least one hardwired pipeline, each hardwired pipeline operable to process respective data without executing program instructions; a communication shell coupled to the hardwired pipelines and operable to transfer data to and from the hardwired pipelines; wherein the first programmable logic integrated circuit further comprises; a communication interface coupled to the interface to the industry standard bus, the communication interface operable to communicate with the interface to the industry standard bus to transfer data to and from the first programmable logic integrated circuit over the industry standard bus, and the communication interface further operable to transfer data to and from each hardwired pipeline via the communication shell. 11. The programmable-circuit unit of claim 10 wherein the first programmable logic integrated circuit is further operable to: receive the first and second different ones of the firmware configurations from an external source via the industry standard bus while operating in a first configuration; and store the first and second different ones of the firmware configurations in the memory while operating in the first configuration. 12. The programmable-circuit unit of claim 10 wherein the first and second programmable logic integrated circuits comprise respective field-programmable gate arrays. 13. A computing machine, comprising: a processor; an industry-standard bus coupled to the processor, the industry-standard bus adapted to be coupled to standard peripheral devices; and a memory that stores a plurality of firmware configurations; and a programmable logic integrated circuit coupled to the memory, and the programmable logic integrated circuit directly coupled to the industry standard bus and through this bus to the processor, the programmable integrated circuit operable to, receive from the processor a new firmware configuration that represents a new configuration of the programmable circuit, store the new firmware configuration in the memory, and download the new firmware configuration from the memory in response to the processor; and wherein the programmable logic integrated circuit further comprises: an interface coupled to the industry standard bus; at least one hardwired pipeline, each hardwired pipeline operable to process respective data without executing program instructions; a communication shell coupled to the hardwired pipelines and operable to transfer data to and from the hardwired pipelines; and a communication interface coupled to the interface to the industry standard bus, the communication interface operable to communicate with the interface to the industry standard bus to transfer data to and from the programmable logic integrated circuit over the industry standard bus, and the communication interface further operable to transfer data to and from each hardwired pipeline via the communication shell. 14. The computing machine of claim 13 wherein the processor is operable to: before sending the new firmware configuration to the programmable logic integrated circuit, determine whether the new firmware configuration is already stored in the memory; and send the new firmware configuration to the programmable circuit only if the firmware is not already stored in the memory. 15. The computing machine of claim 13, further comprising: a configuration registry coupled to the processor and operable to store the new firmware configuration and to indicate that the firmware configuration represents a desired configuration for the programmable circuit; and wherein the processor is operable to download the firmware configuration from the configuration registry to the programmable circuit. 16. The computing machine of claim 13, wherein: the programmable logic integrated circuit includes a hardwired pipeline that is operable to operate on data. 17. A computing machine, comprising: a processor; an industry-standard bus coupled to the processor, the industry-standard bus adapted to be coupled to standard peripheral devices; a memory operable to store a plurality of firmware versions that respectively represent configurations of a programmable logic integrated circuit, the programmable logic integrated circuit being coupled to the memory and being coupled directly to the industry standard bus and through this bus to the processor, the programmable logic integrated circuit operable to, download a selected one of the firmware versions from the memory, operate in the configuration corresponding to the downloaded firmware version, download a different firmware version from the memory in response to the processor, and operate in the configuration corresponding to the different firmware version; wherein the programmable logic integrated circuit further comprises: an interface coupled to the industry standard bus; at least one hardwired pipeline, each hardwired pipeline operable to process respective data without executing program instructions; a communication shell coupled to the hardwired pipelines and operable to transfer data to and from the hardwired pipelines; and a communication interface coupled to the interface to the industry standard bus, the communication interface operable to communicate with the interface to the industry standard bus to transfer data to and from the programmable logic integrated circuit over the industry standard bus, and the communication interface further operable to transfer data to and from each hardwired pipeline via the communication shell. 18. The computing machine of claim 17 wherein: the processor comprises a first test port; the programmable logic integrated circuit comprises a second test port that is coupled to the first test port; and the processor is operable to load the selected one of the firmware versions into memory via the first and second test ports. 19. The computing machine of claim 17 wherein: the processor comprises a first test port; the programmable logic integrated circuit comprises a second test port that is coupled to the first test port; while operating in the configuration corresponding to the selected one of the firmware versions, the programmable logic integrated circuit is operable to perform a self test and to provide self-test data to the processor via the first and second test ports; and the processor is operable to cause the programmable logic integrated circuit to download the different firmware version from memory only if the self-test data indicates a predetermined result of the self test. 20. The computing machine of claim 17 wherein: the processor is operable to send the selected one of the firmware versions to the programmable logic integrated circuit; and while operating in the configuration corresponding to the selected one of the firmware versions, the programmable logic integrated circuit is operable to load the different firmware version into the memory in response to the processor. 21. A computing machine, comprising: a processor; an industry-standard bus coupled to the processor and adapted to be coupled to standard peripheral devices; a memory operable to store a plurality of firmware codes that respectively represent configurations, a first programmable logic integrated circuit coupled to the memory and coupled directly to the industry-standard bus and through this bus to the processor, the first programmable logic integrated circuit operable to, download a first firmware code from the memory, operate in a first configuration corresponding to the first firmware code, download a second firmware code from the memory in response to the processor, and operate in a second configuration corresponding to the second firmware code, and a second programmable logic integrated circuit coupled to the memory and to the first programmable circuit, and coupled through the first programmable logic integrated circuit to the industry-standard bus and through this bus to the processor, the second programmable logic integrated circuit operable to, download a third firmware code from the memory, operate in a third configuration corresponding to the third firmware code, download a fourth firmware code from the memory in response to the processor, and operate in a fourth configuration corresponding to the fourth firmware code; wherein the first programmable logic integrated circuit further comprises: an interface coupled to the industry standard bus; at least one hardwired pipeline, each hardwired pipeline operable to process respective data without executing program instructions; a communication shell coupled to the hardwired pipelines and operable to transfer data to and from the hardwired pipelines; and a communication interface coupled to the interface to the industry standard bus, the communication interface operable to communicate with the interface to the industry standard bus to transfer data to and from the programmable logic integrated circuit over the industry standard bus, and the communication interface further operable to transfer data to and from each hardwired pipeline via the communication shell. 22. The computing machine of claim 21 wherein: while operating in the first configuration, the first programmable logic integrated circuit is operable to perform a first self test and to provide first self-test data to the processor; while operating in the third configuration, the second programmable logic integrated circuit is operable to perform a second self test and to provide second self-test data to the processor; and the processor is operable to cause the first and second programmable circuits to respectively load the second and fourth firmware codes from the memory only if the first and second self-test data indicate respective predetermined results of the first and second self tests. 23. The computing machine of claim 21 wherein: the processor is operable to send the second and fourth firmware codes to the first programmable logic integrated circuit; and while operating in the first configuration, the first programmable logic integrated circuit is operable to load the second and fourth firmware codes into the memory in response to the processor. 24. The computing machine of claim 21 wherein the memory comprises: a first memory section coupled to the first programmable logic integrated circuit and operable to store the first and second firmware codes; and a second memory section coupled to the first and second programmable logic integrated circuits and operable to store the third and fourth firmware codes. 25. The computing machine of claim 24 wherein the first and second memory sections are respectively disposed on first and second integrated circuits. 26. A method, comprising: storing in a memory a plurality of firmware codes, each firmware code representing a configuration of a programmable logic integrated circuit; downloading over an industry-standard bus directly into the programmable logic integrated circuit a first firmware code that represents a first configuration; operating the programmable logic integrated circuit in the first configuration; downloading into the programmable logic integrated circuit second firmware that represents a second configuration; operating the programmable logic integrated circuit in the second configuration after downloading the second firmware; and wherein the firmware that represents the second configuration may only be stored when the programmable logic integrated circuit is operating in the first configuration. 27. The method of claim 26 wherein downloading the second firmware code comprises: sending the second firmware code to the programmable logic integrated circuit; loading the second firmware code into the memory with the programmable logic integrated circuit while the programmable logic integrated circuit is operating in the first configuration; and downloading the second firmware code from the memory into the programmable logic integrated circuit. 28. The method of claim 26 wherein downloading the second firmware code comprises: determining whether the second firmware code is stored in the memory coupled to the programmable logic integrated circuit; sending the second firmware code to the programmable logic integrated circuit only if the second firmware code is not stored in the memory; loading the second firmware code into the memory with the programmable logic integrated circuit while the programmable logic integrated circuit is operating in the first configuration; and downloading the second firmware code from the memory into the programmable logic integrated circuit. 29. The method of claim 26 wherein: operating the programmable logic integrated circuit in the first configuration comprises testing the programmable logic integrated circuit; and downloading the second firmware code comprises downloading the second firmware code only if the programmable logic integrated circuit passes the testing. 30. A method, comprising: storing in memory a plurality of firmware codes, each firmware code defining a corresponding operational configuration for one of first and a second programmable logic integrated circuit; downloading over an industry-standard bus a first and a second one of the firmware codes directly into the first and second programmable logic integrated circuits, respectively; operating the first and second programmable logic integrated circuits in the first and second operational configurations, respectively; downloading a third and a fourth firmware code directly into the first and second programmable logic integrated circuits, respectively, via the first programmable logic integrated circuit; operating the first and second programmable logic integrated circuits in the third configuration and fourth configurations, respectively; and wherein the third and fourth firmware code may only be downloaded when the first and second programmable logic integrated circuits are operating in the first and second operational configurations, respectively. 31. The method of claim 30 wherein: operating the first and second programmable logic integrated circuits in the first and second configurations comprises testing the first and second programmable logic integrated circuits; and loading the third and fourth firmware codes into the first and second programmable logic integrated circuits comprises, loading the third firmware code only if the testing indicates that the first programmable logic integrated circuit is functioning as desired, and loading the fourth firmware code only if the testing indicates that the second programmable logic integrated circuit is functioning as desired.