초록 ▼

A parallel decoder, which is simpler and more flexible than conventional devices, is provided in decoding device for a LDPC code. The present invention includes a plurality of memory units for storing a received value and a message generated during a Message-Passing decoding, a plurality of variable

A parallel decoder, which is simpler and more flexible than conventional devices, is provided in decoding device for a LDPC code. The present invention includes a plurality of memory units for storing a received value and a message generated during a Message-Passing decoding, a plurality of variable node function units, a plurality of check node function units, a plurality of address generation units for generating an address of each of memory units, and a plurality of shuffle network units for determining a connection between variable node function units and check node function units. An address generation unit generates an address on the basis of a plurality of permutations. Each shuffle network unit is connected to some of the variable node function units. This connection is determined on the basis of a plurality of permutations. A change of the permutations in the address generation units and a change of the permutations in the shuffle network units are performed in the same cycle in a decoding process.

대표청구항 ▼

What is claimed is: 1. An error correcting code decoding device based on Message-Passing decoding on a Low-Density Parity-Check Code, whose parity-checkmatrix consists of sub-matrices of a Kronecker product of two permutation matrices, comprising: a plurality of memory means for storing a received

What is claimed is: 1. An error correcting code decoding device based on Message-Passing decoding on a Low-Density Parity-Check Code, whose parity-checkmatrix consists of sub-matrices of a Kronecker product of two permutation matrices, comprising: a plurality of memory means for storing a received value and a message generated during said decoding; a plurality of variable node function means which perform variable node processing in said decoding; a plurality of check node function means which perform check node processing in said decoding; a plurality of address generation means for generating an address of said memory means on the basis of the first permutation matrix of said sub-matrix of a Kronecker product; and a plurality of shuffle network means for determining a connection between said variable node function means on the basis of the second permutation matrix in said sub-matrix of a Kronecker product; wherein said check node functions(s) means perform(s) check node processing sequentially on a unit of said second permutation matrix, and said variable node functions generate messages in accordance with said current check node processing. 2. The error correcting code decoding device according to claim 1, wherein said address generation means singly generate an address for all of said memory means; and wherein said shuffle network means are singly connected to all of said variable node function means. 3. The error correcting code decoding device according to claim 1, wherein said memory means store said message with a sum thereof. 4. The error correcting code decoding device according to claim 1, wherein said address generation means are provided as a counter. 5. The error correcting code decoding device according to claim 1, wherein a second permutation by said shuffle network means is determined on a basis of a Galois field calculation. 6. The error correcting code decoding device according to claim 1, wherein said decoding corrects a message of an output from said check node function means by multiplying the output by a coefficient less than 1 on a basis of a min-sum algorithm. 7. The error correcting code decoding device according to claim 1, wherein in said decoding, said check node function means hold a first minimum value of an absolute value of an input message and an index thereof, and a second minimum value of the input message and information regarding whether the input message is positive or negative on a basis of a min-sum algorithm. 8. The error correcting code decoding device according to claim 1, wherein decoding on a different code is dealt with by changing only said address generation means. 9. The error correcting code decoding device according to claim 1, wherein decoding on a uniform Low-Density Parity-Check Code is implemented by providing a function to always send a message that an output has a codeword bit with an extremely high probability of 0 to a set of said variable node function means corresponding to one of said address generation means and said shuffle network means. 10. An error correcting code decoding method on a basis of Message-Passing decoding on a Low-Density Parity-Check Code, whose parity-checkmatrix consists of sub-matrices of a Kronecker product of a first permutation matrix and a second permutation matrix, the method comprising generating an address of a memory storing a received value and a message generated during said decoding on a basis of the first permutation matrix of said sub-matrix of a Kronecker product; and connecting a plurality of variable node functions in said decoding and a plurality of check node functions in said decoding on a basis of the second permutation matrix of said sub-matrix of a Kronecker product, which is a permutation changed in a same cycle as that of an address generation means; and outputting a decoded error correcting code. 11. The error correcting code decoding method according to claim 10, wherein said memory stores said message with a sum thereof. 12. The error correcting code decoding method according to claim 10, wherein a connection between a variable node function and a check node function is determined on a basis of a Galois field calculation. 13. The error correcting code decoding method according to claim 10, wherein said decoding corrects a message of an output from said check node functions by multiplying the output by a coefficient less than 1 on a basis of a min-sum algorithm. 14. The error correcting code decoding method according to claim 10, wherein in said decoding, said check node functions hold a first minimum value of an absolute value of an input message and an index thereof, and a second minimum value of the input message and information regarding whether the input message is positive or negative on a basis of a min-sum algorithm. 15. The error correcting code decoding method according to claim 10, wherein decoding on a different code is dealt with by changing address generation in memory.