초록 ▼

A programmable logic block provides two lookup table (LUT) output signals to a general interconnect structure in an integrated circuit (IC), one output terminal of the logic block being dedicated to a first LUT output signal, and the other output terminal having a selectable input that can provide e

A programmable logic block provides two lookup table (LUT) output signals to a general interconnect structure in an integrated circuit (IC), one output terminal of the logic block being dedicated to a first LUT output signal, and the other output terminal having a selectable input that can provide either of the two LUT output signals to the general interconnect structure. An IC includes an interconnect structure (e.g., a programmable interconnect structure) and a programmable logic block coupled to the interconnect structure. The programmable logic block includes a LUT having two output terminals. A first LUT output terminal is non-programmably coupled to the interconnect structure via a first output terminal of the logic block. Both the first and the second LUT output terminals are programmably coupled to the interconnect structure via a second output terminal of the logic block, e.g., via a programmable multiplexer selecting between the two LUT output terminals.

대표청구항 ▼

What is claimed is: 1. An integrated circuit, comprising: an interconnect structure; and a programmable logic block comprising: a programmable lookup table (LUT) having a plurality of LUT input terminals coupled to the interconnect structure, a first LUT output terminal non-programmably coupled to

What is claimed is: 1. An integrated circuit, comprising: an interconnect structure; and a programmable logic block comprising: a programmable lookup table (LUT) having a plurality of LUT input terminals coupled to the interconnect structure, a first LUT output terminal non-programmably coupled to the interconnect structure via a first logic block output terminal, and a second LUT output terminal; a first programmable multiplexer having an output terminal coupled to the interconnect structure, a first multiplexer input terminal coupled to the first LUT output terminal, and a second multiplexer input terminal coupled to the second LUT output terminal; a flip-flop having an output terminal coupled to the interconnect structure; and a second programmable multiplexer, the second programmable multiplexer having an output terminal coupled to a data input terminal of the flip-flop, a first multiplexer input terminal coupled to the first LUT output terminal, and a second multiplexer input terminal coupled to the second LUT output terminal. 2. The integrated circuit of claim 1, wherein the programmable logic block further comprises a flip-flop having an input terminal programmably coupled to the first and second LUT output terminals. 3. The integrated circuit of claim 1, wherein the interconnect structure comprises a programmable interconnect structure. 4. The integrated circuit of claim 1, wherein the integrated circuit comprises a field programmable gate array (FPGA). 5. The integrated circuit of claim 1, wherein the interconnect structure comprises a plurality of interconnect lines, and the first logic block output terminal and the output terminal of the first programmable multiplexer drive different interconnect lines within the interconnect structure. 6. The integrated circuit of claim 1, wherein the interconnect structure comprises a plurality of interconnect lines, and none of the interconnect lines in the interconnect structure is driven by both the first logic block output terminal and the output terminal of the first programmable multiplexer. 7. An integrated circuit, comprising: an interconnect structure; and a programmable logic block comprising: a programmable lookup table (LUT) having a plurality of LUT input terminals coupled to the interconnect structure, a first LUT output terminal non-programmably coupled to the interconnect structure via a first logic block output terminal, and a second LUT output terminal; means for programmably selecting exactly one of the first and second LUT output terminals and providing the selected one of the first and second LUT output terminals to the interconnect structure via a second logic block output terminal; a flip-flop having an output terminal coupled to the interconnect structure; and second means for programmably selecting exactly one of the first and second LUT output terminals and providing the selected one of the first and second LUT output terminals to a data input terminal of the flip-flop. 8. The integrated circuit of claim 7, wherein the programmable logic block further comprises a flip-flop having an input terminal programmably coupled to the first and second LUT output terminals. 9. The integrated circuit of claim 7, wherein the interconnect structure comprises a programmable interconnect structure. 10. The integrated circuit of claim 7, wherein the interconnect structure comprises a plurality of interconnect lines, and the first and second logic block output terminals drive different interconnect lines within the interconnect structure. 11. The integrated circuit of claim 7, wherein the interconnect structure comprises a plurality of interconnect lines, and none of the interconnect lines in the interconnect structure is driven by both the first logic block output terminal and the second logic block output terminal.