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In the control section, an operation instruction not prescribing a functional specification, and a unit for processing the specific application-purpose operation instruction is provided within the processor core. The structure of this unit can be changed based on a flexible pipeline structure, and i

In the control section, an operation instruction not prescribing a functional specification, and a unit for processing the specific application-purpose operation instruction is provided within the processor core. The structure of this unit can be changed based on a flexible pipeline structure, and is separately designed for each application field. A register that prescribes a latency from when an instruction of the above unit is issued till when a result can be utilized is also provided in the processor core so as to prevent contention of an output port. Another register that prescribes a latency relating to a constraint of an interval of issuing an instruction of the above unit is also provided in the processor core so as to prevent contention of a resource with the preceding instructions.

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What is claimed is: 1. An information processing apparatus, comprising: a control unit to process an operation instruction, which does not have a functional specification, as a specific application-purpose operation instruction; a specific application-purpose instruction operating unit supporting f

What is claimed is: 1. An information processing apparatus, comprising: a control unit to process an operation instruction, which does not have a functional specification, as a specific application-purpose operation instruction; a specific application-purpose instruction operating unit supporting flexible pipeline processing and carrying an operation of the specific application-purpose operation instruction for each application field; a rewritable register prescribing a number of cycles from when an instruction of said specific application-purpose instruction operating unit is issued until issuance of an immediately subsequent instruction that is same as the instruction of said specific application-purpose instruction operation unit, wherein the instruction of said specific application-purpose instruction operating unit occupies an operating unit source; and a processor core including a flag changing over between a case where a number of cycles, which is prescribed from when an instruction of said specific application-purpose instruction operating unit is issued until issuance of the same instruction in succession, becomes the same as another number of cycles, which is prescribed from when the instruction of the specific application-purpose instruction operating unit is issued a result of the specific application-purpose instruction operating unit is obtained, and a case where the same instruction is issued in succession in each cycle, wherein said control unit controls issuing the instructions based upon the rewritable register and the processor core flag. 2. The information processing apparatus according to claim 1, wherein said specific application-purpose instruction operating unit is built in as an intellectual property of an ASIC (Application Specific Integrated Circuit). 3. The information processing apparatus according to claim 1, wherein the number of cycles control to issue the same succeeding instructions. 4. The information processing apparatus according to claim 1, further comprising: a rewritable register provided within a processor core of the processing apparatus, wherein said rewritable register prescribes a number of cycles from when an instruction of said specific application-purpose instruction operating unit is issued to when it becomes possible to use a result thereof, and said issuing of the instruction is controlled based on said number of cycles. 5. The information processing apparatus according to claim 1, further comprising: a rewritable register provided within a processor core of the processing apparatus, wherein said rewritable register prescribes a number of cycles from when an instruction of said specific application-purpose instruction operating unit is issued to when it becomes possible to issue an immediately subsequent instruction that is the same as the instruction of said specific application-purpose instruction operation unit, and said issuing of the same instruction in succession is controlled based on said number of cycles. 6. An exception processing method for a processor that executes a program including a first instruction and a second instruction, and that performs, after an interruption caused by the second instruction and before execution of an interrupt processing for the second instruction, an exception processing for an exception that has occurred during execution of the first instruction, wherein the first instruction is a specific application-purpose operation instruction, the exception processing method comprising: performing the exception processing for the exception during the execution of the first instruction and before the second instruction interrupt processing, according to a read operation mode indicating to the processor whether to perform the exception processing; setting, when the exception occurs during the execution of the first instruction, a value indicating occurrence of the exception in a register or a flag; determining when the interruption is caused by the second instruction, whether the exception has occurred by reading the register or the flag value; performing the exception processing for the first instruction before the second instruction interrupt processing, upon occurrence of the exception according to the reading of the register or the flag value and returning from the interruption caused by the second instruction by performing the interrupt processing for the second instruction. 7. The exception processing method according to claim 6, further comprising: determining before the execution of the execution processing, whether to perform the exception processing by checking whether the second instruction causing the interruption is a specific application-purpose operation instruction. 8. An exception processing method for a processor that executes a program including a first instruction and a second instruction, and that performs, after an interruption caused by the second instruction and before execution of an interrupt processing for the second instruction, an exception processing for an exception that has occurred during execution of the first instruction, wherein the first instruction is a specific application-purpose operation instruction, the exception processing method comprising: determining before executing the exception processing for the first instruction and before the second instruction interrupt processing, whether to perform the exception processing by checking whether a value, which is stored in a first register or a first flag and associated with the second instruction causing the interruption, indicates to the processor to perform the exception processing; setting, when the exception occurs during the execution of the first instruction, a value indicating occurrence of the exception in a second register or a second flag; determining when the interruption is caused by the second instruction, whether the exception has occurred by reading the second register or the second flag value; performing the exception processing for the first instruction, upon occurrence of the exception according to the reading of the second register or the second flag value and returning from the interruption cased by the second instruction by performing the interrupt processing for the second instruction. 9. An information processing apparatus having a specific application-purpose operation instruction, said information processing apparatus comprising: an operation exception detection flag indicating whether an operation exception has been detected; a specific application-purpose operation instruction executing unit setting said operation exception detection flag to a valid state when an operation exception has been detected during an execution of a specific application-purpose operation instruction; and a flag control unit which notifies an interruption control unit that an interruption due to the operation exception of the specific application-purpose operation instruction is to be generated, when said operation exception detection flag has been set to the valid state during an execution of a trap instruction to generate the interruption, wherein said interruption control unit carries out a control relating to the generation of the interruption, when said interruption control unit has received a notice that the interruption is generated, and when said flag control unit has received an operation exception detection flag invalidate instruction, said flag control unit invalidates said operation exception detection flag indicating an operation exception has not been detected during an execution of a specific application-purpose operation instruction. 10. An information processing apparatus having a specific application-purpose operation instruction, said information processing apparatus comprising: an operation exception detection flag indicating whether an operation exception has been detected; a specific application-purpose operation instruction executing unit setting said operation exception detection flag to a valid state when an operation exception has been detected during an execution of the specific application-purpose operation instruction; and a flag control unit which notifies an interruption control unit that an interruption due to the operation exception of the specific application-purpose operation instruction is to be generated, when said operation exception detection flag has been set to the valid state during an execution of a trap instruction to generate the interruption, wherein said interruption control unit carries out a control relating to the generation of the interruption, when said interruption control unit has received a notice that the interruption is generated, and when said flag control unit has received an operation exception detection flag read instruction, said flag control unit reads a value of said operation exception detection flag for notifying the interruption control unit. 11. An information processing apparatus having a specific application-purpose operation instruction, said information processing apparatus comprising: an operation exception detection flag indicating whether an operation exception has been detected; a specific application-purpose operation instruction executing unit setting said operation exception detection flag to a valid state when an operation exception has been detected during an execution of the specific application-purpose operation instruction; and a flag control unit which notifies an interruption control unit that an interruption due to the operation exception of the specific application-purpose operation instruction is to be generated, when said operation exception detection flag has been set to the valid state during an execution of a trap instruction to generate the interruption, wherein said interruption control unit carries out a control relating to the generation of the interruption, when said interruption control unit has received a notice that the interruption is generated, and when said flag control unit has received an operation exception detection flag write instruction, said flag control unit writes a value into said operation exception detection flag for setting said operation exception detection flag to the valid state. 12. An information processing apparatus having a specific application-purpose operation instruction, said information processing apparatus comprising: an operation exception detection flag indicating whether an operation exception has been detected; a condition code register that is set based on a value that is held in said operation exception detection flag; a specific application-purpose operation instruction executing unit setting said operation exception detection flag to a valid state when the operation exception has been detected during an execution of the specific application-purpose operation instruction; a flag control unit setting the condition code register based on a value that is held in said operation exception detection flag; and a branch/interruption return instruction control unit determining whether an interruption is generated or not based on a value held in said condition code register and a value shown by an instruction field during the execution of a trap instruction to generate the interruption, and, when the interruption is to be generated, notifying an interruption control unit that the interruption due to the operation exception of a specific application-purpose operation instruction is to be generated, wherein said interruption control unit carries out a control relating to the generation of the interruption, when said interruption control unit has received a notice that the interruption is generated. 13. The information processing apparatus according to claim 12, wherein when said flag control unit receives an operation exception detection flag invalidate instruction, said flag control unit invalidates said operation exception detection flag. 14. The information processing apparatus according to claim 12, wherein when said flag control unit receives an operation exception detection flag read instruction, said flag control unit reads the value of said operation exception detection flag. 15. The information processing apparatus according to claim 12, wherein when said flag control unit receives an operation exception detection flag write instruction, said flag control unit writes the value into said operation exception detection flag. 16. The information processing apparatus according to claim 12, wherein said information processing apparatus has an instruction having an operational function specialized for an image processing as the specific application-purpose operation instruction.