Digital intermediate frequency QAM modulator using parallel processing
IPC분류정보
국가/구분
United States(US) Patent
등록
국제특허분류(IPC7판)
H04L-027/36
H04L-027/34
출원번호
US-0644561
(2003-08-19)
등록번호
US-7379509
(2008-05-27)
발명자
/ 주소
Pao,Hsueh Yuan
Tran,Binh Nien
출원인 / 주소
Lawrence Livermore National Security, LLC
대리인 / 주소
Wooldridge,John P.
인용정보
피인용 횟수 :
1인용 특허 :
15
초록▼
The digital Intermediate Frequency (IF) modulator applies to various modulation types and offers a simple and low cost method to implement a high-speed digital IF modulator using field programmable gate arrays (FPGAs). The architecture eliminates multipliers and sequential processing by storing the
The digital Intermediate Frequency (IF) modulator applies to various modulation types and offers a simple and low cost method to implement a high-speed digital IF modulator using field programmable gate arrays (FPGAs). The architecture eliminates multipliers and sequential processing by storing the pre-computed modulated cosine and sine carriers in ROM look-up-tables (LUTs). The high-speed input data stream is parallel processed using the corresponding LUTs, which reduces the main processing speed, allowing the use of low cost FPGAs.
대표청구항▼
We claim: 1. A digital intermediate frequency Quadrature Amplitude Modulation modulator using parallel processing without the use of a multiplier, comprising: a serial-to-parallel data converter operatively connected to receive serial data, wherein said serial-to-parallel data converter converts a
We claim: 1. A digital intermediate frequency Quadrature Amplitude Modulation modulator using parallel processing without the use of a multiplier, comprising: a serial-to-parallel data converter operatively connected to receive serial data, wherein said serial-to-parallel data converter converts a string of serial data to a plurality of parallel data; an I and Q mapper operatively connected to receive said plurality of parallel data and determine its I and Q locations; a plurality of look-up-tables (LUTs) operatively connected to receive and store said I and Q locations, wherein the I LUTs are configured I1 to IN, wherein N is the highest number of I LUTs of said plurality of LUTs, wherein the Q LUTs are configured Q1 to QX, wherein X is the highest number of Q LUTs of said plurality of LUTs; a plurality of adders operatively connected to receive and add said I and Q locations stored within said plurality of LUTs, wherein said plurality of adders are configured A1 to AIQN, wherein IQN is the highest number of adders of said plurality of adders, wherein each I and Q having a particular subscript are added in the adder having the same subscript to produce output data comprising IQ1 to IQIQN; a plurality of registers operatively connected to collect and store said output data comprising IQ1 to IQIQN; and a digital to analog converter operatively connected to convert said output data comprising IQ1 to IQIQN to analog data, wherein said Quadrature Amplitude Modulation modulator does not include a multiplier. 2. A digital intermediate frequency Quadrature Amplitude Modulation modulator using parallel processing without the use of a multiplier, comprising: a serial-to-parallel data converter operatively connected to receive serial data, wherein said serial-to-parallel data converter converts a string of serial data to a plurality of parallel data; an I and Q mapper operatively connected to receive said plurality of parallel data and determine its I and Q locations; a plurality of look-up-tables (LUTs) operatively connected to receive and store said I and Q locations, wherein the I LUTs are configured I1 to IN, wherein N is the highest number of I LUTs of said plurality of LUTs, wherein the Q LUTs are configured Q1 to QX, wherein X is the highest number of Q LUTs of said plurality of LUTs; a plurality of adders operatively connected to receive and add said I and Q locations stored within said plurality of LUTs, wherein said plurality of adders are configured A1 to AIQN, wherein IQN is the highest number of adders of said plurality of adders, wherein each I and Q having a particular subscript are added in the adder having the same subscript to produce output data comprising IQ1 to IQIQN; a plurality of registers operatively connected to collect and store said output data comprising IQ1 to IQIQN; at least one multiplexer operatively connected to collect from said plurality of registers the subscript output data comprising only odd subscript output data from said output data comprising IQ1 to IQIQN; at least one multiplexer operatively connected to collect from said plurality of registers the subscript output data comprising only even subscript output data from said output data comprising IQ1 to IQIQN; and a digital to analog converter operatively connected to convert said odd subscript data and said even subscript data to analog data, wherein said Quadrature Amplitude Modulation modulator does not include a multiplier. 3. The digital intermediate frequency Quadrature Amplitude Modulation modulator using parallel processing without the use of a multiplier of claim 2, wherein said at least one multiplexer operatively connected to collect from said plurality of registers the subscript output data comprising only odd subscript output data from said output data comprising IQ1 to IQIQN comprises n��2 multiplexers, where n is an integer, and wherein said at least one multiplexer is operatively connected to collect from said plurality of registers the subscript output data comprising only even subscript output data from said output data comprising IQ1 to IQIQN comprises n��2 multiplexers. 4. A digital intermediate frequency Quadrature Amplitude Modulation modulator using parallel processing without the use of a multiplier, comprising: a plurality of look-up-tables (LUTs) operatively connected to receive and store I and Q locations, wherein the I LUTs are configured I1 to IN, wherein N is the highest number of I LUTs of said plurality of LUTs, wherein the Q LUTs are configured Q1 to QX, wherein X is the highest number of Q LUTs of said plurality of LUTs; a plurality of adders operatively connected to receive and add said I and Q locations stored within said plurality of LUTs, wherein said plurality of adders are configured A1 to AIQN, wherein IQN is the highest number of adders of said plurality of adders, wherein each I and Q having a particular subscript are added in the adder having the same subscript to produce output data comprising IQ1 to IQIQN; a plurality of registers operatively connected to coiled and store said output data comprising IQ1 to IQIQN; a first multiplexer operatively connected to collect from said plurality of registers only odd subscript output data from said output data comprising IQ1 to IQIQN; a second multiplexer operatively connected to collect from said plurality of registers only even subscript output data from said output data comprising IQ1 to IQIQN; and a digital to analog converter operatively connected to convert said odd subscript data and said even subscript data to analog data, wherein said Quadrature Amplitude Modulation modulator does not include a multiplier. 5. The digital intermediate frequency Quadrature Amplitude Modulation modulator using parallel processing without the use of a multiplier of claim 4, wherein said first multiplexer comprises n��2 multiplexers, where n is an integer, and wherein said second multiplexer comprises n��2 multiplexers. 6. A digital intermediate frequency Quadrature Amplitude Modulation modulator using parallel processing without the use of a multiplier comprising: a plurality of look-up-tables (LUTs) operatively connected to receive and store I and Q locations, wherein the I LUTs are configured I1 to IN, wherein N is the highest number of I LUTs of said plurality of LUTs, wherein the Q LUTs are configured Q1 to QX, wherein X is the highest number of Q LUTs of said plurality of LUTs; a plurality of adders operatively connected to receive and add said I and Q locations stored within said plurality of LUTs, wherein said plurality of adders are configured A1 to AIQN, wherein IQN is the highest number of adders of said plurality of adders, wherein each I and Q having a particular subscript are added in the adder having the same subscript to produce output data comprising IQ1 to IQIQN; a plurality of registers operatively connected to collect and store said output data comprising IQ1 to IQIQN; and a digital to analog converter operatively connected to convert said output data comprising IQ1 to IQIQN to analog data, wherein said Quadrature Amplitude Modulation modulator does not include a multiplier. 7. A method for processing data with a digital intermediate frequency QAM modulator using parallel processing without the use of a multiplier, comprising: receiving and converting a string of serial data into a plurality of parallel data; determining the I and Q locations of said plurality of parallel data; storing said I and Q locations in a plurality of look-up-tables (LUTs), wherein the I LUTs are configured I1 to IN, wherein N is the highest number of I LUTs of said plurality of LUTs, wherein the Q LUTs are configured Q1 to QX, wherein X is the highest number of Q LUTs of said plurality of LUTs; receiving and adding said I and Q locations stored within said plurality of LUTs, wherein a plurality of adders are configured A1 to AIQN, wherein IQN is the highest number of adders of said plurality of adders, wherein each I and Q having a particular subscript are added in the adder having the same subscript to produce output data comprising IQ1 to IQIQN; collecting and storing said output data comprising IQ1 to IQIQN in a plurality of registers; and converting said output data comprising IQ1 to IQIQN to analog data in a digital to analog converter, wherein said Quadrature Amplitude Modulation modulator does not include a multiplier. 8. A method for processing data in a digital intermediate frequency QAM modulator using parallel processing without the use of a multiplier, comprising: receiving and converting a string of serial data to a plurality of parallel data; receiving said plurality of parallel data in an I and Q mapper and determine the I and Q locations of said plurality of parallel data; receiving and storing said I and Q locations in a plurality of look-up-tables (LUTs), wherein the I LUTs are configured I1 to IN, wherein N is the highest number of I LUTs of said plurality of LUTs, wherein the Q LUTs are configured Q1 to QX, wherein X is the highest number of Q LUTs of said plurality of LUTs; receiving and adding said I and Q locations stored within said plurality of LUTs in a plurality of adders, wherein said plurality of adders are configured A1 to AIQN, wherein IQN is the highest number of adders of said plurality of adders, wherein each I and Q having a particular subscript are added in the adder having the same subscript to produce output data comprising IQ1 to IQIQN; collecting and storing in a plurality of registers said output data comprising IQ1 to IQIQN; collecting, in a first multiplexer, from said plurality of registers, the subscript output data comprising only odd subscript output data from said output data comprising IQ1 to IQIQN; collecting, in a second multiplexer, from said plurality of registers, the subscript output data comprising only even subscript output data from said output data comprising IQ1 to IQIQN; and converting, a digital to analog converter, said odd subscript data and said even subscript data to analog data, wherein said Quadrature Amplitude Modulation modulator does not include a multiplier. 9. The method of claim 8, wherein said first multiplexer comprises n��2 multiplexers, where n is an integer, and wherein said second multiplexer comprises n��2 multiplexers. 10. A method for processing data in a digital intermediate frequency QAM modulator using parallel processing without the use of a multiplier, comprising: receiving and storing in a plurality of look-up-tables (LUTs), I and Q locations, wherein the I LUTs are configured I1 to IN, wherein N is the highest number of I LUTs of said plurality of LUTs, wherein the Q LUTs are configured Q1 to QX, wherein X is the highest number of Q LUTs of said plurality of LUTs; receiving and adding in a plurality of adders said I and Q locations stored within said plurality of LUTs, wherein said plurality of adders are configured A1 to AIQN, wherein IQN is the highest number of adders of said plurality of adders, wherein each I and Q having a particular subscript are added in the adder having the same subscript to produce output data comprising IQ1 to IQIQN; collecting and storing in a plurality of registers said output data comprising IQ1 to IQIQN; collecting in a first multiplexer only odd subscript output data from said output data comprising IQ1 to IQIQN; collecting in a second multiplexer only even subscript output data from said output data comprising IQ1 to IQIQN; and converting in a digital to analog converter said odd subscript data and said even subscript data to analog data, wherein said Quadrature Amplitude Modulation modulator does not include a multiplier. 11. The method of claim 10, wherein said first multiplexer comprises n��2 multiplexers, where n is an integer, and wherein said second multiplexer comprises n��2 multiplexers. 12. A method for processing data with a digital intermediate frequency Quadrature Amplitude Modulation modulator using parallel processing without the use of a multiplier, comprising: receiving and storing, in a plurality of look-up-tables (LUTs) I and Q locations, wherein the I LUTs are configured I1 to IN, wherein N is the highest number of I LUTs of said plurality of LUTs, wherein the Q LUTs are configured Q1 to QX, wherein X is the highest number of Q LUTs of said plurality of LUTs; receiving and adding in a plurality of adders said I and Q locations stored within said plurality of LUTs, wherein said plurality of adders are configured A1 to AIQN, wherein IQN is the highest number of adders of said plurality of adders, wherein each I and Q having a particular subscript are added in the adder having the same subscript to produce output data comprising IQ1 to IQIQN; collecting and storing in a plurality of registers said output data comprising IQ1 to IQIQN; and converting in a digital to analog converter said output data comprising IQ1 to IQIQN to analog data, wherein said Quadrature Amplitude Modulation modulator does not include a multiplier.
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