Method and apparatus for timing modeling is described. More particularly, wire information, including wire lengths, is obtained from a routing output. Signals associated with such wire information are classified as input or output signals from an embedded core. Respective templates are automatically
Method and apparatus for timing modeling is described. More particularly, wire information, including wire lengths, is obtained from a routing output. Signals associated with such wire information are classified as input or output signals from an embedded core. Respective templates are automatically selected for the input signals and the output signals, respectively, at least in partial response to the wire lengths. Furthermore, timing information for the embedded core is obtained and classified according to condition, and the input signals and the output signals from the embedded core are determined to obtain rise and fall timing information for such signals.
대표청구항▼
The invention claimed is: 1. A method for selection of a simulation template, comprising: obtaining a wire length and an associated signal name; determining whether the wire length is for a signal originating from an embedded core in response to the associated signal name, the embedded core being a
The invention claimed is: 1. A method for selection of a simulation template, comprising: obtaining a wire length and an associated signal name; determining whether the wire length is for a signal originating from an embedded core in response to the associated signal name, the embedded core being a microprocessor, the embedded core having been designed separately from a host integrated circuit in which the embedded core is embedded; if the wire length is not for carrying the signal originating from the embedded core, selecting a wire line model for at least one conductive line associated with the wire length; selecting a driver in at least partial response to the associated signal name, the associated signal name having signal source information specifying driver type used; selecting the simulation template in response to the driver selected, the simulation template being one of a plurality of simulation templates, the simulation template being at the resistor-transistor level; iteratively repeating the selecting of the wire line model, the driver, and the simulation template for each of a plurality of drivers in a circuit; and simulating operation of the circuit using each said simulation template selected to generate timing information, wherein the circuit is gasket logic for coupling the embedded core to circuitry of the host integrated circuit. 2. The method according to claim 1, wherein the simulation template is a network list. 3. The method according to claim 2, wherein the network list is for an HSpice simulation. 4. A method for selection of a simulation template, comprising: obtaining a wire length and an associated signal name; determining whether the wire length is for a signal originating from an embedded core in response to the associated signal name, the embedded core being a microprocessor, the embedded core having been designed separately from a host integrated circuit in which the embedded core is embedded; if the wire length is for carrying the signal originating from the embedded core, determining an adjusted wire length from the wire length; determining if the adjusted wire length is less than a predetermined length; selecting the simulation template in response to whether the adjusted wire length is less than the predetermined length, the simulation template being at the resistor-transistor level; and simulating operation of a circuit using the simulation template to generate timing information, the circuit being gasket logic for coupling the embedded core to circuitry of the host integrated circuit. 5. The method according to claim 4, further comprising setting the adjusted wire length less than the predetermined length to the predetermined length. 6. The method according to claim 4, wherein the step of determining the adjusted wire length comprises subtracting a load wire length from the wire length. 7. The method according to claim 6, wherein the step of subtracting comprises converting a capacitive output load of the embedded core into the load wire length. 8. The method according to claim 4, wherein the predetermined length is determined from a clock period. 9. The method according to claim 8, wherein the clock period is converted into the predetermined length in part by determining signal propagation delay through at least one conductive line. 10. A method for selection of simulation templates, comprising: obtaining wire lengths and associated signal names; determining whether the wire lengths are for signals originating from an embedded core in response to the associated signal names, the embedded core being a microprocessor, the embedded core having been designed separately from a host integrated circuit in which the embedded core is embedded; for the wire lengths not for carrying the signals originating from the embedded core which are for carrying signaling to the embedded core, selecting wire line models for conductive lines associated with the wire lengths; selecting from a first group of simulation templates; for the wire lengths for carrying the signals originating from the embedded core, determining adjusted wire lengths from the wire lengths; determining if the adjusted wire lengths are less than a predetermined length; selecting from a second group of simulation templates in response to a first portion of the adjusted wire lengths being less than the predetermined length; selecting from a third group of simulation templates in response to a second portion of the adjusted wire lengths not being less than the predetermined length; and simulating operation of a circuit using the simulation templates selected from the first group of simulation templates, the second group of simulation templates, and the third group of simulation templates to generate timing information, the circuit being gasket logic for coupling the embedded core to circuitry of the host integrated circuit, and the simulation templates selected being at the resistor-transistor level. 11. The method according to claim 10, wherein the first group of simulation templates, the second group of simulation templates and the third group of simulation templates each comprise at least one network list. 12. The method according to claim 11, wherein the at least one network list is for HSpice simulation. 13. A tangible computer-readable storage medium having stored thereon computer-executable instructions for performing a method of selecting simulation templates, the method comprising steps of: accessing a wire length and an associated signal name; determining whether the wire length is for a signal originating from an embedded core in response to the associated signal name, the embedded core being a microprocessor, the embedded core having been designed separately from a host integrated circuit in which the embedded core is embedded; if the wire length is not for carrying the signal originating from the embedded core, a. selecting a wire line model for at least one conductive line associated with the wire length; b. selecting a driver in at least partial response to the associated signal name, the associated signal name having signal source information specifying driver type used; c. selecting a first simulation template in response to the driver selected; if the wire length is for carrying the signal originating from the embedded core, d. determining an adjusted wire length from the wire length; e. determining if the adjusted wire length is less than a predetermined length; f. selecting a second simulation template in response to whether the adjusted wire length is less than the predetermined length; simulating operation of a circuit using the first simulation template selected and the second simulation template selected to generate timing information; iteratively repeating steps a, b, and c for selection of a plurality of first simulation templates responsive to a plurality of drivers in the circuit, the plurality of drivers including the driver; iteratively repeating steps d, e, and f for selection of a plurality of second simulation templates responsive to a plurality of wire lengths in the circuit, the plurality of wire lengths including the wire length; and the simulated operation of the circuit being responsive to the plurality of first simulation templates selected and the plurality of second simulation templates selected, the circuit being gasket logic for coupling the embedded core to circuitry of the host integrated circuit, and the first plurality of simulation templates and the second plurality of simulation templates selected being at the resistor-transistor level.
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Freeman ; deceased Ross H. (late of San Jose CA by Dennis Hersey ; executor), Configurable electrical circuit having configurable logic elements and configurable interconnects.
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DeHon Andre ; Knight ; Jr. Thomas F. ; Tau Edward ; Bolotski Michael ; Eslick Ian ; Chen Derrick ; Brown Jeremy, Dynamically programmable gate array with multiple contexts.
Hartmann Alfred C., Dynamically reconfigurable logic networks interconnected by fall-through FIFOs for flexible pipeline processing in a system-on-a-chip.
Agrawal Om P. ; Chang Herman M. ; Sharpe-Geisler Bradley A. ; Nguyen Bai, FPGA integrated circuit having embedded SRAM memory blocks and interconnect channel for broadcasting address and control signals.
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Agrawal Om P. ; Sharpe-Geisler Bradley A. ; Tran Giap H., Flexible direct connections between input/output blocks (IOBs) and variable grain blocks (VGBs) in FPGA integrated circ.
Colwell Robert P. (Portland OR) Papworth David B. (Beaverton OR) Fetterman Michael A. (Hillsboro OR) Glew Andrew F. (Hillsboro OR) Hinton Glenn J. (Portland OR) Coward Stephen M. (Aloha OR) Chen Grac, Hybrid execution unit for complex microprocessor.
Andrews William B. ; Britton Barry K. ; Hickey Thomas J. ; Modo Ronald T. ; Nguyen Ho T. ; Schadt Lorraine L. ; Singh Satwant, Hybrid programmable gate arrays.
Gilson Kent L. (255 N. Main St. ; Apt. 210 Salt Lake City UT 84115), Integrated circuit computing device comprising a dynamically configurable gate array having a microprocessor and reconfi.
Gilson Kent L. (Salt Lake City UT), Integrated circuit computing device comprising a dynamically configurable gate array having a microprocessor and reconfi.
Lien Jung-Cheun ; Feng Sheng ; Sun Chung-yuan ; Huang Eddy Chieh, Integrated circuit that includes a field-programmable gate array and a hard gate array having the same underlying structure.
Sutherland James (Santa Clara CA) Garverick Timothy L. (Cupertino CA) Takiar Hem P. (Fremont CA) Reyling ; Jr. George F. (Saratoga CA), Logical three dimensional interconnections between integrated circuit chips using a two dimensional multi-chip module.
Rostoker Michael D. (Boulder Creek CA) Gluss David (Woodside CA) Harrington Tom (Mountain View CA), Method and apparatus for interim, in-situ testing of an electronic system with an inchoate ASIC.
Jose Maria Insenser Farre ES; Julio Faura Enriquez ES, Microprocessor based mixed signal field programmable integrated device and prototyping methodology.
Barry K. Britton ; Ravikumar Charath ; Zheng Chen ; James F. Hoff ; Cort D. Lansenderfer ; Don McCarley ; Richard G. Stuby, Jr. ; Ju-Yuan D. Yang, Multi-master multi-slave system bus in a field programmable gate array (FPGA).
Ang, Roger; Ahuja, Atul; Lulla, Mukesh T.; Borkovic, Drazen; Small, Brian D.; Tralka, Charles C.; Chan, Andrew K.; Yee, Kevin K., Programmable device with an embedded portion for receiving a standard circuit design.
Kimura Junichi (Hachiouji JPX) Nejime Yoshito (Hachiouji JPX) Noguchi Kouji (Kokubunji JPX), Programmable digital signal processor for performing a plurality of signal processings.
Cliff Richard G. (Milpitas CA) Cope L. Todd (San Jose CA) McClintock Cameron R. (Mountain View CA) Leong William (San Fransisco CA) Watson James A. (Santa Clara CA) Huang Joseph (San Jose CA) Ahanin , Programmable logic array integrated circuits.
Patel, Rakesh H.; Turner, John E., Technique of fabricating integrated circuits having interfaces compatible with different operating voltage conditions.
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