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A method and a system for transferring data between a register in a processor and a point-to-point communications link. More specifically, blocking and non-blocking methods are described to get and put data between a general purpose register of a soft or hard core processor and a queue connected to

A method and a system for transferring data between a register in a processor and a point-to-point communications link. More specifically, blocking and non-blocking methods are described to get and put data between a general purpose register of a soft or hard core processor and a queue connected to a point-to-point communications channel. One implementation example is for a Fast Simplex Link multi-processor network.

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What is claimed is: 1. A method for a processor getting data from a queue, the processor, comprising a status register having a flag indicating an arithmetic carry, configured to execute a plurality of instructions, the method comprising: coupling the processor to an input queue storing data receiv

What is claimed is: 1. A method for a processor getting data from a queue, the processor, comprising a status register having a flag indicating an arithmetic carry, configured to execute a plurality of instructions, the method comprising: coupling the processor to an input queue storing data received by way of a point-to-point communication channel from a second processor; receiving an empty indication at an inverter; receiving an inverted output of the inverter and an asserted value at an AND gate, when an instruction executed by the processor is a non-blocking get instruction; producing, by the AND gate, the value of the flag of the status register; when the input queue is not empty of data, assuring that the flag stored in the status register located in the processor is equal to a predetermined value; reading an item of data from the input queue received by way of the point-to-point communication channel, if the flag is equal to the predetermined value; coupling the item of data to a general purpose register of the first processor; and executing an instruction of the plurality of instructions executed by the first processor based upon the value of the flag. 2. The method of claim 1 wherein the instruction is an arithmetic instruction, and further comprising, a second instruction of the plurality of instructions, the second instruction using a result of the arithmetic instruction to determine if a branch to a third instruction of the plurality of instructions is taken. 3. The method of claim 2 wherein the arithmetic instruction is an add with carry or a subtract with carry instruction used by a microprocessor configured on a field programmable gate array. 4. The method of claim 1 wherein the reading an item of data from the input queue comprises: sending a read request to the input queue; and receiving the item of data from the input queue. 5. The method of claim 1 further comprising: when the input queue is empty of data, setting the flag to another predetermined value. 6. A system for getting data via a communications link comprising: an input queue, comprising an empty indication, coupled to a point-to-point communication channel for receiving an item of data from a first processor; an inverter receiving an empty indication and producing an inverted output; an AND gate receiving the inverted output and an asserted value, when an instruction executed by the processor is a non-blocking get instruction, and producing the value of a carry flag; a second processor, coupled to the input queue and comprising a plurality of registers, for using the item of data; a general purpose register of the plurality of registers, coupled to the input queue receiving the item of data by way of the point-to-point communication channel, for storing the item of data; and a second register of the plurality of registers, comprising a status register of the second processor having the carry flag configured for evaluation by an arithmetic instruction executed by the second processor, wherein a value of the carry flag is based on the empty indication. 7. The system of claim 6 wherein the input queue is a fast simplex link (FSL) first-in-first-out (FIFO) queue. 8. The system of claim 6 wherein the value of the carry flag is a function of the empty indication and a predetermined value for a get instruction, wherein when the get instruction is executed by the second processor, the item of data is loaded from the input queue to the general purpose register. 9. The system of claim 8 wherein the function is a Boolean and includes a NOT and an AND function. 10. A system for putting data via a communications link comprising: a queue, comprising a full indication, coupled to the communications link for sending an item of data; a processor, comprising a plurality of registers, for using the item; a first register of the plurality of registers coupled to the queue, the first register configured to store the item for transfer to the queue; and second register of the plurality of registers, comprising a carry flag configured for evaluation by an arithmetic instruction executed by the processor, wherein a value of the carry flag is based on the full indication; an inverter receiving the full indication and producing an inverted output; and an AND gate receiving the inverted output and an asserted value, when an instruction executed by the processor is a non-blocking put instruction, and producing the value of the carry flag. 11. A fast linked multiprocessor network, comprising: a plurality of processing modules, wherein each processing module of said plurality of processing modules comprises a status register and a general purpose register; and a selector circuit coupled between the general purpose register of a processor and a plurality of queues; a plurality of configurable uni-directional links coupled among a plurality of queues of a first processing module and a plurality of queues of a second processing module of the plurality processing modules, the plurality of configurable unidirectional links providing communications channels between the first processing module and the second processing module; wherein a configurable uni-directional link of the plurality of configurable uni-directional links comprises an output queue of the first processing module at a first end of a communications channel and an input queue of the second processing module at a second end of the communications channel; wherein the status register of the first processing module of the plurality of processing modules includes a flag having an indication if the input queue is not empty; an inverter receiving a full indication from the output queue and producing an inverted output; and an AND gate receiving the inverted output and an asserted value, when an instruction executed by the processor is a non-blocking put instruction, and producing the value of the flag of the status register of the first processing module of the plurality of processing modules. 12. The fast linked multiprocessor network of claim 11 further comprising an OR gate coupled to the output of the AND gate and another indication and configured to set the flag. 13. The fast linked multiprocessor network of claim 11 wherein the input queue is a first-in-first-out (FIFO) queue and the output queue is another first-in-first-out (FIFO) queue. 14. The fast linked multiprocessor network of claim 11 further comprising: a data item sent from the general purpose register of the first processing module of the plurality of processing modules to the general purpose register of a second processing module of the plurality of processing modules via the configurable uni-directional link of the plurality of configurable unidirectional links. 15. The fast linked multiprocessor network of claim 14 wherein the data item comprises a control bit. 16. The fast linked multiprocessor network of claim 14 wherein the data item comprises a data word and an additional bit set by the first processing module. 17. The fast linked multiprocessor network of claim 11 wherein a processing module of plurality of processing modules is configure in a field programmable gate array (FPGA). 18. A system for getting data from a processor, configured to execute a plurality of instructions, the system comprising: a plurality of point-to-point communication channels coupled between a first processor and a second processor; an input queue coupled to a general purpose register of the first processor and to receive data from a second processor by way of a point-to-point communication channel of the plurality of point-to-point communication channels, the first processor having a status register; when the input queue is not empty of data, means for setting a flag of the status register to a predetermined value comprising an inverter receiving an empty indication and producing an inverted output; and an AND gate receiving the inverted output and an asserted value, when an instruction executed by the processor is a non-blocking get instruction, and producing the value of the flag of the status register; means for reading an item of data from the input queue received from the second processor by way of the point-to-point communication channel, if the flag is equal to the predetermined value; and means for executing an instruction of the plurality of instructions executed by the processor based upon the value of the flag.