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Transferring data using direct memory access 원문보기

IPC분류정보
국가/구분 United States(US) Patent 등록
국제특허분류(IPC7판)
  • G06F-012/08
출원번호 US-0484460 (2002-11-07)
등록번호 US-7380115 (2008-05-27)
국제출원번호 PCT/US02/035786 (2002-11-07)
§371/§102 date 20040115 (20040115)
국제공개번호 WO03/043254 (2003-05-22)
발명자 / 주소
  • Maine,Gene
출원인 / 주소
  • Dot Hill Systems Corp.
대리인 / 주소
    Sheridan Ross P.C.
인용정보 피인용 횟수 : 13  인용 특허 : 35

초록

A direct memory access (DMA) engine has virtually all control in connection with data transfers that can involve one or both of primary and secondary controllers. The DMA engine receives a command related to a data transfer from a processor associated with the primary controller. This command causes

대표청구항

What is claimed is: 1. A method for processing data, comprising: providing at least a first controller communicable with a remote memory, said first controller including a direct memory access (DMA) engine; providing at least a processor communicating with a processor memory; storing information us

이 특허에 인용된 특허 (35)

  1. Wilcox Jeffrey, Address triggered DMA controller with an indicative signal including circuitry for calculating a new trigger address value based on the sum of the current trigger address and the descriptor register .
  2. Surugucchi Krishnakumar Rao ; George Geeta, Apparatus and method for coupling devices to a PCI-to-PCI bridge in an intelligent I/O controller.
  3. Smith Michael G. (Tustin CA), Automatic control of distributed DMAs in a PCI bus system supporting dual ISA buses.
  4. Okazawa Koichi (Tokyo JPX) Kimura Koichi (Yokohama JPX) Kawaguchi Hitoshi (Yokohama JPX) Aburano Ichiharu (Hitachi JPX) Kobayashi Kazushi (Ebina JPX) Mochida Tetsuya (Yokohama JPX), Bus system for use with information processing apparatus.
  5. Pecone, Victor Key, Bus zoning in a channel independent storage controller architecture.
  6. Herbert Brian K., DMA controller of a RAID storage controller with integrated XOR parity computation capability adapted to compute parity in parallel with the transfer of data segments.
  7. Busser, Richard W.; Davies, Ian R., Data mirroring using shared buses.
  8. Brian Arsenault ; Victor W. Tung ; Jeffrey Stoddard Kinne, Data storage system.
  9. Iwami Hiroyuki (Yokohama JPX), Data transfer unit for small computer system with simultaneous transfer to two memories and error detection and rewrite.
  10. Tawfik David A. (Woodcliff Lake NJ) Doniger Jerry (Montvale NJ) Porawski Donald J. (Cedar Grove NJ), Digital flight guidance system.
  11. Sgammato, Frank J., Dynamic port mode selection for crosspoint switch.
  12. Tim Teitenberg ; Bikram Singh Bakshi, Efficient memory management for channel drivers in next generation I/O system.
  13. Nielson Michael E. (Broomfield CO) Brant William A. (Boulder CO) Neben Gary (Boulder CO), Fault tolerant memory system which utilizes data from a shadow memory device upon the detection of erroneous data in a m.
  14. Abraham Menachem (Lexington MA) Bartolini David (Dudley MA) Ben-Meir Samuel (Sharon MA) Carmi Ilan (Framingham MA) Cook ; III John L. (Southborough MA) Hart Ira (Cambridge MA) Herman Alex (Sharon MA), Generic backplane system which is configurable to serve different network access methods simultaneously.
  15. Marks Randal S. ; Roberson Randy L. ; Shen Diana ; Sicola Stephen J., Host transparent storage controller failover/failback of SCSI targets and associated units.
  16. Glenn A. Baxter, Intelligent direct memory access controller providing controlwise and datawise intelligence for DMA transfers.
  17. Shek Edde Tang Tin ; Stubbs Robert E., Interrupt mechanism on NorthBay.
  18. Chan Jong, Memory controller supporting redundant synchronous memories.
  19. Diehl Michael R. ; Hammond Maynard, Method and apparatus for performing direct memory access transfers involving non-sequentially-addressable memory locations.
  20. Gugel, Robert Glenn, Method and system for data transfer.
  21. James W. Meyer, Method of checking data integrity for a RAID 1 system.
  22. Pecone Victor Key ; Swanson Dwayne Howard, Modular bus bridge system compatible with multiple bus pin configurations.
  23. Jibbe Mahmoud K. (Wichita KS) McCombs Craig C. (Wichita KS) Thompson Kenneth J. (Wichita KS), Multiple configuration data path architecture for a disk array controller.
  24. Narad Charles E. ; Fall Kevin ; MacAvoy Neil ; Shankar Pradip ; Rand Leonard M. ; Hall Jerry J., Packet processing system including a policy engine having a classification unit.
  25. Liron Moshe (Evanston IL), Peripheral unit controller.
  26. Lui Albert S. ; Naminski Ronald John ; Oliver James Wesley ; Aster Radek ; Wood Neill Preston, Raid system with fibre channel arbitrated loop.
  27. Chow, Yan Chiew; Hsia, James R., Real time local and remote management of data files and directories and method of operating the same.
  28. Fromm Eric C. (Eau Claire WI), Recursive address centrifuge for distributed memory massively parallel processing systems.
  29. Young Paul R. (Cromwell CT) Solari Peter L. (Lebanon CT) Shumski Gregory J. (Colchester CT) So Yin Cheung (Fremont CA), Redundant array of solid state memory devices.
  30. Browne Hendrik A., Secure computer system and method of providing secure access to a computer system including a stand alone switch operable to inhibit data corruption on a storage device.
  31. Shrader Steven L. ; Rust Robert A., Storage management system and auto-RAID transaction manager for coherent memory map across hot plug interface.
  32. Steven L. Shrader ; Robert A. Rust, Storage management system and auto-RAID transaction manager for coherent memory map across hot plug interface.
  33. Meyer James W., System and method for providing a fast and efficient comparison of cyclic redundancy check (CRC/checks sum) values of two mirrored disks.
  34. Phillip M. Jones ; Robert Allan Lester, System for identifying memory requests as noncacheable or reduce cache coherence directory lookups and bus snoops.
  35. Christensen Steven G. (Minneapolis MN), TDM digital matrix intercom system.

이 특허를 인용한 특허 (13)

  1. Pandya, Ashish A., 100GBPS security and search architecture using programmable intelligent search memory.
  2. Moyer, William C., Access extent monitoring for data transfer reduction.
  3. Starr, Matthew Thomas, Data deduplication in a removable storage device.
  4. Ybarra, Danny O.; Thomas, Jeffrey O., Data manipulation engine.
  5. Pandya, Ashish A., Distributed network security system and a hardware processor therefor.
  6. Pandya, Ashish A., Dynamic random access memory (DRAM) that comprises a programmable intelligent search memory (PRISM) and a cryptography processing engine.
  7. Pandya, Ashish A., High performance IP processor using RDMA.
  8. Pandya, Ashish A., High performance IP processor using RDMA.
  9. Pandya, Ashish A, IP storage processor and engine therefor using RDMA.
  10. Ananthabhotla, Anand, Method and system for zero-copy disk IO using sector unaligned buffers.
  11. Pandya, Ashish A., Programmable intelligent search memory (PRISM) and cryptography engine enabled secure DRAM.
  12. Pandya, Ashish A., Programmable intelligent search memory enabled secure flash memory.
  13. Lu, Xiangfeng, Writing data using DMA by specifying a buffer address and a flash memory address.
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