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A design is used for coordinating channel bonding operations of a set of transceivers. The set include a master transceiver and a plurality of first level slave transceivers that perform channel bonding operations. Each first level transceiver is controlled by the master transceiver. The set also co

A design is used for coordinating channel bonding operations of a set of transceivers. The set include a master transceiver and a plurality of first level slave transceivers that perform channel bonding operations. Each first level transceiver is controlled by the master transceiver. The set also comprises a plurality of second level slave transceivers that perform channel bonding operations. Each second level transceiver is controlled by one of the plurality of first level transceivers. Any transceiver can be set as either a master, a first level slave or a second level slave. The design comprises a plurality of flip-flops and multiplexers, and is controlled by a MODE signal that determines the mode of operation of the design.

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The invention claimed is: 1. A system for coordinating channel bonding operations of a plurality of transceivers of an integrated circuit, comprising: a master transceiver of the integrated circuit that performs channel bonding operations for aligning different portions of a data stream transmitted

The invention claimed is: 1. A system for coordinating channel bonding operations of a plurality of transceivers of an integrated circuit, comprising: a master transceiver of the integrated circuit that performs channel bonding operations for aligning different portions of a data stream transmitted in parallel by way of a plurality of data channels; a plurality of first level transceivers of the integrated circuit that perform channel bonding operations, each first level transceivers being controlled by the master transceiver and receiving a control signal by way of a first configurable path, wherein the first configurable path is configured according to a first mode signal for a first level transceiver, the first mode signal determining a delay of the control signal received by way of the first configurable path; and a plurality of second level transceivers of the integrated circuit that perform channel bonding operations, each second level transceiver being controlled by one of the plurality of first level transceivers and receiving a control signal by way of a second configurable path, wherein the second configurable path is configured according to a second mode signal for a second level transceiver, the second mode signal determining a delay of the control signal received by way of the second configurable path; wherein each transceiver comprises a controller receiving a mode control signal designating the transceiver as a master transceiver or a slave transceiver and enabling a control signal to be applied to the transceiver by way of a configurable path during a predetermined clock cycle to enable channel bonding operations for aligning the different portions of the data stream transmitted in parallel. 2. The system of claim 1 further comprising a clock signal, and wherein the master transceiver and the plurality of first level transceivers generate respective control signals at different cycles of the clock signal. 3. The system of claim 1 wherein each of the plurality of transceivers contains at least one buffer for the channel bonding operations. 4. An apparatus that generates an output signal in response to a first input signal and a second input signal comprising control signals for aligning data, the apparatus comprising: a first flip-flop that accepts the first input signal and generate an output signal; a first multiplexer having an output terminal and at least a first and a second input terminal, the first input terminal accepting the output signal of the first flip-flop, and the second input terminal being connected to the second input signal; a second flip-flop having an output terminal and an input terminal that connects with the output terminal of the first multiplexer; a second multiplexer having an output terminal and at least a first and a second input terminal, the first input terminal being connected to the output terminal of the second flip-flop, and the second input terminal being connected to the second input signal; and a third flip-flop having an output terminal and an input terminal, the input terminal being connected to the output terminal of the second multiplexer. 5. The apparatus of claim 4 further comprising: a third multiplexer having an output terminal and at least a first and a second input terminal, the first input terminal being connected to the first input signal, the second input terminal being connected to the second input signal; and a fourth flip-flop having an output terminal and an input terminal, the input terminal being connected to the output terminal of the third multiplexer. 6. A communication system comprising: a first device having a plurality of transceivers; and a second device having a plurality of transceivers; wherein the plurality of transceivers in the first device is connected to the plurality of transceivers in the second device which receives control signals for aligning data received from the first device; and each of the transceivers comprises: a buffer, a first flip-flop that accepts a first input signal and generate an output signal; a first multiplexer having an output terminal and at least a first and a second input terminal, the first input terminal accepting the output signal of the first flip-flop, and the second input terminal being connected to a second input signal; a second flip-flop having an output terminal and an input terminal that connects with the output terminal of the first multiplexer; a second multiplexer having an output terminal and at least a first and a second input terminal, the first input terminal being connected to the output terminal of the second flip-flop, and the second input terminal being connected to the second input signal; and a third flip-flop having an output terminal to control the buffer and an input terminal, the input terminal being connected to the output terminal of the second multiplexer. 7. The system of claim 6 wherein each of the transceivers further comprises: a third multiplexer having an output terminal and at least a first and a second input terminal, the first input terminal being connected to the first input signal, the second input terminal being connected to the second input signal; and a fourth flip-flop having an output terminal and an input terminal, the input terminal being connected to the output terminal of the third multiplexer. 8. The system of claim 1 wherein the system for coordinating channel bonding operations of a plurality of transceivers comprises a system for aligning bytes of a word. 9. The system of claim 1 wherein said transceivers comprise a plurality of levels, where each slave transceiver comprises an input to receive a control signal from a previous level. 10. The system of claim 9 wherein each slave transceiver is configured by mode control signal to receive a control signal from either a master transceiver or a slave transceiver. 11. The apparatus of claim 4 wherein the first input signal comprises a master input signal. 12. The apparatus of claim 4 wherein the second input signal comprises a control signal from a previous stage. 13. The apparatus of claim 4 wherein the output of said second multiplexer of a transceiver comprises a control signal for the transceiver. 14. The apparatus of claim 5 wherein the output of the fourth flip-flop of a transceiver comprises a control signal coupled to another transceiver. 15. The system of claim 6 wherein the communication system comprises N levels of devices having a plurality of transceivers. 16. The system of claim 15 wherein a path from an input of a control circuit of a master transceiver to an output of the control circuit generating a control signal coupled to the master transceiver comprises N flip flops. 17. The system of claim 16 wherein each level of transceivers following the master transceiver comprises N-X flip flops where X comprises the number of stages after the master transceiver. 18. The system of claim 17 wherein the communication system comprises a field programmable gate array.