IPC분류정보
국가/구분 |
United States(US) Patent
등록
|
국제특허분류(IPC7판) |
|
출원번호 |
US-0276639
(2006-03-08)
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등록번호 |
US-7385240
(2008-06-10)
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발명자
/ 주소 |
- Fazan,Pierre C.
- Mathews,Viju K.
|
출원인 / 주소 |
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대리인 / 주소 |
Schwegman, Lundberg & Woessner, P.A.
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인용정보 |
피인용 횟수 :
0 인용 특허 :
59 |
초록
▼
An integrated circuit structure includes a digit line and an electrode adapted to be part of a storage cell capacitor and includes a barrier layer interposed between a conductive plug and an oxidation resistant layer. An insulative layer protects sidewalls of the barrier layer during deposition and
An integrated circuit structure includes a digit line and an electrode adapted to be part of a storage cell capacitor and includes a barrier layer interposed between a conductive plug and an oxidation resistant layer. An insulative layer protects sidewalls of the barrier layer during deposition and anneal of a dielectric layer. The method includes forming the conductive plug recessed in an insulative layer. The barrier layer is formed in the recess and the top layer. An oxidation resistant conductive layer and a further oxide layer are formed in the recess. The conductive layer is planarized to expose the oxide or oxide/nitride layer. The oxide layers are then etched to expose the top surface and vertical portions of the conductive layer. A dielectric layer is formed to overlie the storage node electrode. A cell plate electrode is fabricated to overlie the dielectric layer.
대표청구항
▼
What is claimed is: 1. An integrated circuit structure, comprising: a buried digit line; and an electrode operatively connected to the buried digit line, the electrode including: a first portion formed in an insulative layer having an upper surface; a second portion overlying the first portion, whe
What is claimed is: 1. An integrated circuit structure, comprising: a buried digit line; and an electrode operatively connected to the buried digit line, the electrode including: a first portion formed in an insulative layer having an upper surface; a second portion overlying the first portion, wherein said insulative layer surrounds a sidewall of said second portion and said second portion does not extend above the upper surface; and a third portion overlying said second portion and, extending above and below said upper surface of said insulative layer, and including a recess, wherein said first portion and said second portion are different materials, wherein said first portion is a silicon contact. 2. The integrated circuit structure of claim 1, wherein the second portion and the third portion are different materials. 3. The integrated circuit structure of claim 2, wherein the first portion and the third portion are different materials. 4. The integrated circuit structure of claim 1, wherein the buried digit line includes a patterned digit line conductive layer and a patterned strapping layer. 5. The integrated circuit structure of claim 4, wherein the strapping layer is adapted to reduce an overall resistance of the digit lines. 6. The integrated circuit structure of claim 1, wherein the buried digit line includes WSix. 7. The integrated circuit structure of claim 1, wherein the buried digit line includes TiN. 8. The integrated circuit structure of claim 1, wherein the buried digit line includes doped polysilicon. 9. The integrated circuit structure of claim 1, wherein the digit lines are formed prior to the electrode. 10. An integrated circuit structure, comprising: a buried digit line including at least one from the group consisting essentially of WSix and TiN; and an electrode operatively connected to the buried digit line, the electrode including: a first portion formed in an insulative layer having an upper surface, wherein said first portion is a silicon contact; a second portion overlying the first portion, wherein said insulative layer surrounds a sidewall of said second portion and said second portion does not extend above the upper surface, wherein the second portion and the first portion are different materials; and a third portion overlying said second portion and, extending above and below said upper surface of said insulative layer, and including a recess, and wherein the third portion and the second portion are different materials. 11. The integrated circuit structure of claim 10, wherein the buried digit line includes a patterned digit line conductive layer and a patterned strapping layer. 12. The integrated circuit structure of claim 11, wherein the strapping layer is adapted to reduce an overall resistance of the digit lines. 13. An integrated circuit structure, comprising: a buried digit line adapted to electrically communicate with external circuitry; an electrode operatively connected to the buried digit line, the electrode including: a first portion formed in an insulative layer having an upper surface; a second portion overlying the first portion, wherein the insulative layer surrounds a sidewall of the second portion and the second portion does not extend above the upper surface; and a third portion overlying said second portion and, extending above and below said upper surface of said insulative layer, and including a recess, wherein said first portion and said second portion are different materials, wherein said second portion is a diffusion barrier layer prohibiting diffusion of atoms between said first and said third portions. 14. The integrated circuit structure of claim 13, wherein the buried digit line includes at least one from the group consisting essentially of WSix and TiN. 15. The integrated circuit structure of claim 13, wherein the buried digit line includes a patterned digit line conductive layer and a patterned strapping layer adapted to reduce an overall resistance of the digit line. 16. An integrated circuit structure, comprising: a digit line; a capacitor operatively connected to the digit line, the capacitor including an electrode having: a first portion formed in an insulative layer having an upper surface; a second portion overlying the first portion, wherein said insulative layer surrounds a sidewall of said second portion and said second portion does not extend above the upper surface; and a third portion overlying said second portion and, extending above and below said upper surface of said insulative layer, and including a recess, wherein said first portion and said second portion are different materials, wherein said third portion is an oxidation resistant layer. 17. The integrated circuit structure of claim 16, wherein said insulative layer surrounds a lower sidewall of said third portion. 18. The integrated circuit structure of claim 16, wherein the digit line is adapted to connected to an address producing circuit of a memory device, and wherein the capacitor is a storage device for the memory device. 19. The integrated circuit structure of claim 18, wherein the memory device is a random access memory. 20. The integrated circuit structure of claim 16, wherein the digit line includes WSix. 21. The integrated circuit structure of claim 16, wherein the digit line includes TiN. 22. The integrated circuit structure of claim 16, wherein the capacitor includes a dielectric layer overlying the third portion; and a cell plate electrode overlying the dielectric layer. 23. The integrated circuit structure of claim 16, wherein the capacitor is operatively connected to the digit line through a transistor. 24. An integrated circuit structure, comprising: a digit line; a capacitor operatively connected to the digit line, the capacitor including an electrode having: a contact formed in an insulative layer having an upper surface; a diffusion barrier portion overlying said contact, said insulative layer surrounding a sidewall of said diffusion barrier portion and said diffusion barrier portion not extending above said upper surface; and an oxidation resistant portion overlying said diffusion barrier portion and, extending above and below said upper surface of said insulative layer, and including a recess, said diffusion barrier portion configured to inhibit diffusion of atoms between said contact and said oxidation resistant portion. 25. The integrated circuit structure of claim 24, wherein the digit line includes WSix. 26. The integrated circuit structure of claim 24, wherein the digit line includes TiN. 27. The integrated circuit structure of claim 24, wherein the capacitor includes a dielectric layer overlying the third portion; and a cell plate electrode overlying the dielectric layer. 28. The integrated circuit structure of claim 27, wherein the first portion of the electrode is operatively connected to the digit line through a transistor. 29. The integrated circuit structure of claim 24, wherein the buried digit line includes a patterned digit line conductive layer and a patterned strapping layer adapted to reduce an overall resistance of the digit line. 30. An integrated circuit structure, comprising: a digit line including at least one from the group consisting essentially of WSix and TiN; a capacitor operatively connected to the digit line, the capacitor including an electrode having: a first portion formed in an insulative layer having an upper surface; a second portion overlying the first portion, wherein said insulative layer surrounds a sidewall of said second portion and said second portion does not extend above the upper surface; and a third portion overlying said second portion, extending above and below said upper surface of said insulative layer, and including a recess, wherein said first portion and said second portion respectively consist essentially of polysilicon and tantalum. 31. The integrated circuit structure of claim 30, wherein the third portion consists essentially of platinum. 32. The integrated circuit structure of claim 11, wherein the insulative layer is a single layer.
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