Method and apparatus for testing loop pathway integrity in a fibre channel arbitrated loop
원문보기
IPC분류정보
국가/구분
United States(US) Patent
등록
국제특허분류(IPC7판)
H04L-012/26
H04L-001/00
H04L-001/16
H04J-001/16
H04J-001/00
H04J-003/14
G01R-031/08
G06F-011/00
G08C-015/00
출원번호
US-0889551
(2004-07-12)
등록번호
US-7388843
(2008-06-17)
발명자
/ 주소
Fike,John M
Wen,William J.
Hareski,Patricia E
Allada,Sudhakar V.
출원인 / 주소
QLogic, Corporation
대리인 / 주소
Klein, O'Neill & Singh, LLP
인용정보
피인용 횟수 :
4인용 특허 :
119
초록▼
A method for performing a fibre channel arbitrated loop integrity test using a fibre channel switch element is provided. The method includes, sending a fibre channel frame through the arbitrated loop; receiving the fibre channel frame after it has traversed through the arbitrated loop; performing a
A method for performing a fibre channel arbitrated loop integrity test using a fibre channel switch element is provided. The method includes, sending a fibre channel frame through the arbitrated loop; receiving the fibre channel frame after it has traversed through the arbitrated loop; performing a data compare between the fibre channel frame that was sent and the fibre channel frame that is received; detecting internal errors, if any, in the traversed fibre channel loop; and isolating a module that may have generated the error. The switch element includes, a cascade port that is used to couple one fibre channel switch element to another in a loop; and a port that sends a fibre channel frame through the loop and detects internal errors based on the comparison and a isolates a module that may have generated the internal error.
대표청구항▼
What is claimed: 1. A method for performing an integrity test in a fibre channel arbitrated loop in order to determine whether any errors are present in the loop, the loop including a fibre channel switch element the method comprising: sending a fibre channel frame through the arbitrated loop: rece
What is claimed: 1. A method for performing an integrity test in a fibre channel arbitrated loop in order to determine whether any errors are present in the loop, the loop including a fibre channel switch element the method comprising: sending a fibre channel frame through the arbitrated loop: receiving the fibre channel frame after it has traversed the arbitrated loop; performing a data compare between the fibre channel frame that was sent and the fibre channel frame that is received; detecting internal errors, if any, in the switch element; and if an internal error is detected, isolating a port that generated the error; wherein the step of sending the frame through the arbitrated loop comprises sending the frame through a plurality of ports within the switch, the ports being connected in series with a receive path of one port being connected to a transmit path of a next port. 2. The method of claim 1, wherein the step of detecting internal errors is performed in a transmission protocol engine (TPE) port of the fibre channel switch element. 3. The method of claim 2, wherein a parity detector checks for pant errors on a transmit path of the TPE port. 4. The method of claim 3, wherein a Cyclic Redundancy Code (CRC) checker checks for CRC errors on a receive path of the TPE port. 5. The method of claim 1, wherein plural fibre channel switch elements are coupled to each other using a cascade port and the fibre channel frame traverses the plural fibre channel switch elements. 6. The method of claim 5, further comprising detecting interconnection data path errors between the fibre channel switch elements, if no internal errors are detected. 7. The method of claim 6, wherein the step of detecting interconnection data path errors between the fibre channel switch elements comprises successively removing each switch element from the loop and performing the integrity test until the test fails. 8. The method of claim 1, wherein a TPE port of the switch element sends the fibre channel frame to a successive TPE port of the switch element. 9. The method of claim 1, wherein a frame manager module of the switch element receives the fibre channel frame after it has traversed the arbitrated loop. 10. The method of claim 9, wherein the frame manager module comprises a Small Computer System Interface (SCSI) Enclosure Services (SES) module. 11. A fibre channel switch element coupled to an arbitrated loop, the switch element comprising: a cascade port configured to couple the fibre channel switch element to a second fibre channel switch element in a loop; a plurality of transmission protocol engine (TPE) ports within the first switch element, the TPE ports being connected in series with a receive path of one port being connected to a transmit path of a next port; and a frame manager module configured to send a fibre channel frame through the loop, to compare the fibre channel frame that was sent and the fibre channel frame that is received, to detect internal errors, if any, in the first switch element based on the comparison, and to isolate a TPE port that generated the internal error. 12. The fibre channel switch element of claim 11, wherein the frame manager module is configured to detect inter-connection data path errors between the fibre channel switch elements, if the comparison reveals no internal errors. 13. The fibre channel switch element of claim 12. wherein the frame manager module comprises a Small Computer System Interface (SCSI) Enclosure Services (SES) module. 14. A system for performing integrity tests in a fibre channel arbitrated loop, the system comprising: a plurality of fibre channel switch elements cascaded in a loop; a first one of the fibre channel switch elements including a plurality of transmission protocol engine (TPE) ports, the TPE ports being connected in series with a receive path of one port being connected to a transmit path of a next port; and the first switch element further including a host port, a cascade port, and a frame manager module for performing diagnostic services, wherein the frame manager module is configured to send a fibre channel frame through the loop, to compare the fibre channel frame that was sent and the fibre channel frame that is received, to detect internal errors, if any, in the first switch element based on the comparison, and to isolate a TPE port that generated the internal error. 15. The system of claim 14, wherein the frame manager module is further configured to detect inter-connection data path errors between the fibre channel switch elements, if the comparison reveals no internal errors. 16. The system of claim 15, wherein the frame manager module comprises a Small Computer System Interface (SCSI) Enclosure Services (SES) module.
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Acampora Anthony S. (Freehold NJ) Naghshineh Mahmoud (Fishkill NY), Method and apparatus for supporting mobile communications in asynchronous transfer mode based networks.
Johnson, Stephen M.; Hoglund, Timothy E.; Weber, David M.; Adams, John M.; Reber, Mark A., Method and apparatus for transmitting data to a node in a distributed data processing system.
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Lu, Tan; Casper, Daniel F.; Craddock, David F.; Dugan, Robert J.; Frazier, Giles R., Method for pacing buffered data transfers over a network such as fibre channel.
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Walter Chris J. (Columbia MD) Kieckhafer Roger M. (Lincoln NE) Finn Alan M. (Amston CT), Operations controller for a fault tolerant multiple node processing system.
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Anderson Craig D. ; Anderson Mark B. ; Cookmeyer Eugene N. ; Daniels Ralph A. ; Wheat Lee E. ; Lingle Roger A., Protocol analyzer for monitoring digital transmission networks.
Bass Brian M. ; Henderson Douglas Ray ; Ku Edward Hau-chun ; Lemke Scott J. ; Rash Joseph M. ; Reiss Loren Blair ; Ryle Thomas Eric, Simultaneous cut through and store-and-forward frame support in a network device.
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Sheldon,Robert D.; Maples,Benton B.; Gott,Terri J., System and method for identifying errors in a video conference conducted on a packet-based network.
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Schreiner Stanley M. (Stamford CT) Benua Susan E. (Newtown CT) Van Raalte Peter (Wilton CT) Ambrose David (Monroe CT), Time multiplexed bus matrix switching system.
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