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An electronic module is provided. The module includes a first logic device having at least two processors and a first comparator and a second logic device having at least one processor and a second comparator. Each of the at least two processors are coupled to each of the first and second comparator

An electronic module is provided. The module includes a first logic device having at least two processors and a first comparator and a second logic device having at least one processor and a second comparator. Each of the at least two processors are coupled to each of the first and second comparators. The first and second comparators operate as a distributed comparator system. Each comparator independently identifies faults in the processors.

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What is claimed is: 1. A system comprising: a first logic device having at least two processors and a first comparator; and a second logic device having at least one processor and a second comparator; wherein each of the at least two processors are coupled to each of the first and second comparator

What is claimed is: 1. A system comprising: a first logic device having at least two processors and a first comparator; and a second logic device having at least one processor and a second comparator; wherein each of the at least two processors are coupled to each of the first and second comparators; wherein the first and second comparators operate as a distributed comparator system; wherein each comparator independently identifies faults in the processors. 2. The system of claim 1, wherein the first and second logic devices are programmable. 3. The system of claim 1, wherein each of the first and second comparators perform a comparison function in software. 4. The system of claim 1, wherein each of the first and second comparators is a hardware device. 5. The system of claim 1, wherein each of the first and second logic devices is a field programmable gate array. 6. A logic device comprising: at least three processors that are adapted to perform substantially the same function; at least one hardware comparator comprising: a binary comparator; a control logic device coupled to the binary comparator; a selector coupled to the control logic device; and a broadcaster coupled to the selector; wherein each of the at least three processors includes a software implemented fault tolerance function (SIFT); wherein each of the at least three SIFTs is communicatively coupled to the at least one hardware comparator; and wherein each of the SIFTs operates independently of each other to identify faults in one or more of the at least three processors; wherein the logic device is configured to: perform a first portion of a comparison function using each of the SIFTs; perform a second portion of the comparison function using the hardware comparator; forward results from the second portion of the comparison function to each of the SIFTs; and combine results of each of the first portion of the comparison function and the second portion of the comparison function. 7. The logic device in claim 6, wherein the logic device is programmable. 8. The logic device of claim 6, wherein the logic device is a field programmable gate array. 9. The logic device in claim 6, wherein the hardware comparator is radiation hardened. 10. A system comprising: a logic device having at least three processors; and at least one hardware comparator coupled to each of the at least three processors, the hardware comparator comprising: a binary comparator; a control logic device coupled to the binary comparator; a selector coupled to the control logic device; and a broadcaster coupled to the selector; wherein each processor includes a software implemented fault tolerance (SIFT) function; wherein the SIFT and the at least one hardware comparator in combination processes outputs of the at least three processors; wherein the SIFT determines if one or more of the at least three processors has failed; wherein the logic device is configured to: perform a first portion of a comparison function using each SIFT; perform a second portion of the comparison function using the hardware comparator; retrieve results of each of the first portion of the comparison function and the second portion of the comparison function; and forward results from the second portion of the comparison function to each SIFT. 11. The system of claim 10, wherein the logic device is programmable. 12. The system of claim 10, wherein the logic device is a field programmable gate array. 13. The system of claim 10, wherein the at least one hardware comparator is radiation hardened. 14. A method for identifying a fault in a programmable device having at least three redundant processors each having a software implemented fault tolerance (SIFT) function, the method comprising: generating an output at each of the at least three redundant processors; receiving the generated outputs at each of the SIFTs; performing a first portion of a comparison function using each of the SIFTs; performing a second portion of the comparison function using a hardware comparator; forwarding results from the second portion of the comparison function to each of the SIFTs; combining results of each of the first portion of the comparison function and the second portion of the comparison function; and analyzing the combined results, wherein the analysis comprises: performing a voting function of the combined results, comprising checking for a minority vote; and determining faulty processors among the at least three redundant processors based on the minority vote. 15. The method of claim 14, further comprising initializing the faulty processor when a minority vote is achieved. 16. The method in claim 14, wherein the hardware comparator is radiation hardened. 17. The method in claim 14, wherein the programmable device is a field programmable gate array. 18. A method for accelerating a voting mechanism in a programmable device having at least three redundant processors each having a software implemented fault tolerance (SIFT) function, the method comprising: generating an output in each of the at least three redundant processors; receiving the generated outputs at each of the SIFTs; performing a first portion of a comparison function using each of the SIFTs; performing a second portion of the comparison function using a hardware comparator; retrieving results of each of the first portion of the comparison function and the second portion of the comparison function; and forwarding results from the second portion of the comparison function to each of the SIFTs. 19. The method of claim 18, wherein the hardware comparator is radiation hardened. 20. The method of claim 18, wherein the programmable device is a field programmable gate array. 21. The method of claim 18, wherein the programmable device is an application specific integrated chip. 22. An electronic module, comprising: a first logic device having at least two processors and a first comparator; and a second logic device having at least one processor and a second comparator; wherein each of the at least two processors are coupled to each of the first and second comparators; wherein the first and second comparators operate as a distributed comparator system; wherein each comparator independently identifies faults in the processors; wherein the logic devices are combined on a single chip. 23. The electronic module of claim 22, wherein the first and second logic devices are programmable. 24. The electronic module of claim 22, wherein each of the first and second comparators perform a comparison function in software. 25. The electronic module of claim 22, wherein each of the first and second comparators are hardware devices. 26. The electronic module of claim 22, wherein each of the first and second logic devices is a field programmable gate array. 27. A machine readable medium having instructions stored thereon for identifying a fault in a programmable device having at least three redundant processors each having a software implemented fault tolerance (SIFT) function, the method comprising: generating an output at each of the at least three redundant processors; receiving the generated outputs at each of the SIFTs; performing a first portion of a comparison function using each of the SIFTs; performing a second portion of the comparison function using a hardware comparator; forwarding results from the second portion of the comparison function to each of the SIFTs; combining results of each of the first portion of the comparison function and the second portion of the comparison function; and analyzing the combined results, wherein the analysis comprises: performing a voting of the combined results comprising checking for a minority vote; and determining faulty processors among the at least three redundant processors based on the minority vote. 28. The method of claim 27, further comprising initializing the faulty processor when a minority vote is achieved. 29. The method of claim 27, wherein the programmable device is a field programmable gate array. 30. A machine readable medium having instructions stored thereon for accelerating a voting mechanism in a programmable device having at least three redundant processors each having a software implemented fault tolerance (SIFT) function, the method comprising: generating an output in each of the at least three redundant processors; receiving the generated outputs at each of the SIFTs; performing a first portion of a comparison function using each of the SIFTs; performing a second portion of the comparison function using a hardware comparator; retrieving results of each of the first portion of the comparison function and the second portion of the comparison function; and forwarding results from the second portion of the comparison function to each of the SIFTs. 31. The method of claim 30, wherein the hardware comparator is radiation hardened. 32. The method of claim 30, wherein the programmable device is a field programmable gate array. 33. The method of claim 30, wherein the programmable device is an application specific integrated chip.