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Capping of metal interconnects in integrated circuit electronic devices 원문보기

IPC분류정보
국가/구분 United States(US) Patent 등록
국제특허분류(IPC7판)
  • H01L-021/44
  • H01L-021/02
출원번호 US-0852513 (2007-09-10)
등록번호 US-7393781 (2008-07-01)
발명자 / 주소
  • Yakobson,Eric
  • Hurtubise,Richard
  • Witt,Christian
  • Chen,Qingyun
출원인 / 주소
  • Enthone Inc.
대리인 / 주소
    Senniger Powers LLP
인용정보 피인용 횟수 : 4  인용 특허 : 44

초록

A multilayer metal cap over a metal-filled interconnect feature in a dielectric layer for incorporation into a multilayer integrated circuit device, and a method for forming the cap.

대표청구항

What is claimed is: 1. A method for forming a multilayer metal cap over a metal-filled interconnect feature in a dielectric layer for incorporation into a multilayer integrated circuit device comprising: depositing a first cobalt-based metal cap layer over the metal-filled interconnect feature in a

이 특허에 인용된 특허 (44)

  1. Shacham Yosef Y. (Ithaca NY) Bielski Roman (Ithaca NY), Alkaline free electroless deposition.
  2. Lopatin Sergey D. ; Cheung Robin W., Apparatus and method of encapsulated copper (Cu) Interconnect formation.
  3. Farooq Mukta S. (Hopewell Junction NY) Kaja Suryanarayana (Hopewell Junction NY) Perfecto Eric D. (Poughkeepsie NY) White George E. (Hoffman Estates IL), Capped copper electrical interconnects.
  4. Farooq Mukta Shaji ; Kaja Suryanarayana ; Perfecto Eric Daniel ; White George Eugene, Capped copper electrical interconnects.
  5. Farooq Mukta Shaji ; Kaja Suryanarayana ; Perfecto Eric Daniel ; White George Eugene, Capped copper electrical interconnects.
  6. Lee Chwan-Ying,TWX ; Huang Tzuen-Hsi,TWX, Copper metallization of USLI by electroless process.
  7. Semkow Krystyna W. ; O'Sullivan Eugene J., Corrosion protection for metallic features.
  8. Edelstein Daniel C. ; Dalton Timothy J. ; Gaudiello John G. ; Krishnan Mahadevaiyer ; Malhotra Sandra G. ; McGlashan-Powell Maurice ; O'Sullivan Eugene J. ; Sambucetti Carlos J., Dual etch stop/diffusion barrier for damascene interconnects.
  9. Dubin Valery M. ; Shacham-Diamand Yosef ; Ting Chiu H. ; Zhao Bin ; Vasudev Prahalad K., Electroless CU deposition on a barrier layer by CU contact displacement for ULSI applications.
  10. Inoue, Hiroaki; Nakamura, Kenji; Matsumoto, Moriji; Ezawa, Hirokazu; Miyata, Masahiro; Tsujimura, Manabu, Electroless Ni--B plating liquid, electronic device and method for manufacturing the same.
  11. Ting Chiu H. (Saratoga CA) Paunovic Milan (Port Washington NY), Electroless deposition for IC fabrication.
  12. Vratny ; Frederick, Electroless deposition of nickel on a masked aluminum surface.
  13. Hongo, Akihisa; Mishima, Koji; Inoue, Hiroaki; Kimura, Norio; Karimata, Tsutomu, Electroless plating apparatus and method.
  14. Chebiam, Ramanan V.; Dubin, Valery M., Electroless plating bath composition and method of using.
  15. Inoue, Hiroaki; Nakamura, Kenji; Matsumoto, Moriji, Electroless plating liquid and semiconductor device.
  16. Dubin, Valery M.; Thomas, Christopher D.; McGregor, Paul; Datta, Madhav, Interconnect structures and a method of electroless introduction of interconnect structures.
  17. Lopatin Sergey D., Low resistivity semiconductor barrier layer manufacturing method.
  18. Pavlov, Michael; Chalyt, Gene; Bratin, Peter; Kogan, Alex; Perpich, Michael James, Measurement of the concentration of a reducing agent in an electroless plating bath.
  19. Sambucetti Carlos Juan ; Rubino Judith Marie ; Edelstein Daniel Charles ; Cabral ; Jr. Cyryl ; Walker George Frederick ; Gaudiello John G ; Wildman Horatio Seymour, Method for forming Co-W-P-Au films.
  20. Sambucetti, Carlos Juan; Rubino, Judith Marie; Edelstein, Daniel Charles; Cabral, Jr., Cyryl; Walker, George Frederick; Gaudiello, John G; Wildman, Horatio Seymour, Method for forming Co-W-P-Au films.
  21. Farooq Mukta S. (Hopewell Junction NY) Kaja Suryanarayana (Hopewell Junction NY) Perfecto Eric D. (Poughkeepsie NY) White George E. (Hoffman Estates IL), Method for forming capped copper electrical interconnects.
  22. Zeller Faith M. (Eagan MN), Method of coating copper conductors on polyimide with a corrosion resistant metal, and module produced thereby.
  23. Dubin, Valery M.; Thomas, Christopher D.; McGregor, Paul; Datta, Madhav, Method of electroless introduction of interconnect structures.
  24. Daniel C. Edelstein ; Timothy J. Dalton ; John G. Gaudiello ; Mahadevaiyer Krishnan ; Sandra G. Malhotra ; Maurice McGlashan-Powell ; Eugene J. O'Sullivan ; Carlos J. Sambucetti, Method of forming barrier layers for damascene interconnects.
  25. Ogure, Naoaki; Inoue, Hiroaki, Method of forming embedded copper interconnections and embedded copper interconnection structure.
  26. Cyprian E. Uzoh ; Daniel C. Edelstein ; Cheryl Faltermeier ; Peter S. Locke, Method to build multi level structure.
  27. Edelstein, Daniel C.; Kang, Sung Kwon; McGlashan-Powell, Maurice; O'Sullivan, Eugene J.; Walker, George F., Method to selectively cap interconnects with indium or tin bronzes and/or oxides thereof and the interconnect so capped.
  28. Edelstein, Daniel C.; Kang, Sung Kwon; McGlashan-Powell, Maurice; O'Sullivan, Eugene J.; Walker, George F., Method to selectively cap interconnects with indium or tin bronzes and/or oxides thereof and the interconnect so capped.
  29. Ivanov, Igor C.; Zhang, Weiguo, Methods and system for processing a microelectronic topography.
  30. Cheng,Chin Chang; Dubin,Valery M., Multiple stage electroless deposition of a metal layer.
  31. Kaja Suryanarayana (Hopewell Junction NY) Mukherjee Shyama P. (Hopewell Junction NY) O\Sullivan Eugene J. (Upper Nyack NY) Paunovic Milan (Port Washington NY), Palladium sulfate solution for the selective seeding of the metal interconnections on polyimide dielectrics for electrol.
  32. Yamamoto, Naoko; Yamamoto, Tatsushi; Hirayama, Masaki; Ohmi, Tadahiro, Plasma processing apparatus.
  33. Naoki Komai JP; Yuji Segawa JP; Takeshi Nogami JP, Process for fabricating a semiconductor device.
  34. Kaja Suryanarayana (Hopewell Junction NY) O\Sullivan Eugene J. (Nyack NY) Schrott Alejandro G. (New York NY), Process for fabricating improved multilayer interconnect systems.
  35. Schacham-Diamand Yosef ; Dubin Valery M. ; Ting Chiu H. ; Zhao Bin ; Vasudev Prahalad K. ; Desilva Melvin, Protected encapsulation of catalytic layer for electroless copper interconnect.
  36. Paul R. Besser ; Darrell M. Erb ; Sergey Lopatin, Selective deposition process for passivating top interface of damascene-type Cu interconnect lines.
  37. Zhao Bin (Austin TX) Vasudev Prahalad K. (Austin TX) Dubin Valery M. (Cupertino CA) Shacham-Diamand Yosef (Ithaca NY) Ting Chiu H. (Saratoga CA), Selective electroless copper deposited interconnect plugs for ULSI applications.
  38. Georgiou George E. (Gillette NJ) Poli Gary N. (High Bridge NJ), Selective electroless plating of vias in VLSI devices.
  39. Edelstein, Daniel C.; Stamper, Anthony K.; Rubino, Judith M.; Sambucetti, Carlos J., Self-aligned corrosion stop for copper C4 and wirebond.
  40. Nakano, Hiroshi; Itabashi, Takeyuki; Akahoshi, Haruo, Semiconductor device having cobalt alloy film with boron.
  41. Lopatin Sergey D. ; Pramanick Shekhar ; Brown Dirk, Semiconductor metalization barrier.
  42. Mathew, Varughese; Garcia, Sam S.; Prindle, Christopher M., Semiconductor process and composition for forming a barrier material overlying copper.
  43. Dubin Valery M. (Cupertino CA) Schacham-Diamand Yosi (Ithaca NY) Zhao Bin (Irvine CA) Vasudev Prahalad K. (Austin TX) Ting Chiu H. (Saratoga CA), Use of cobalt tungsten phosphide as a barrier material for copper metallization.
  44. Dubin,Valery M.; Cheng,Chin Chang; Hussein,Makarem; Nguyen,Phi L.; Brain,Ruth A., Use of conductive electrolessly deposited etch stop layers, liner layers and via plugs in interconnect structures.

이 특허를 인용한 특허 (4)

  1. Lin, Yu-Hung; Lin, Sheng-Hsuan; Chang, Chih-Wei; Chou, You-Hua; Hsu, Chia-Lin, Composite contact plug structure and method of making same.
  2. Lin, Yu-Hung; Lin, Sheng-Hsuan; Chang, Chih-wei; Chou, You-Hua; Hsu, Chia-Lin, Composite contact plug structure and method of making same.
  3. Gambino, Jeffrey P.; He, Zhong-Xiang; Lee, Tom C., Isolated wire structures with reduced stress, methods of manufacturing and design structures.
  4. Gambino, Jeffrey P.; He, Zhong-Xiang; Lee, Tom C., Isolated wire structures with reduced stress, methods of manufacturing and design structures.
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