초록 ▼

An SOI wafer is constructed from a carrier wafer and a monocrystalline silicon layer having a thickness of less than 500 nm, an excess of interstitial silicon atoms prevailing in the entire volume of the silicon layer. The SOI wafers may be prepared by Czochralski silicon single crystal growth, the

An SOI wafer is constructed from a carrier wafer and a monocrystalline silicon layer having a thickness of less than 500 nm, an excess of interstitial silicon atoms prevailing in the entire volume of the silicon layer. The SOI wafers may be prepared by Czochralski silicon single crystal growth, the condition v/Gcrit=1.3��10-3 cm2/(K��min) being fulfilled at the crystallization front over the entire crystal cross section, with the result that an excess of interstitial silicon atoms prevails in the silicon single crystal produced; separation of at least one donor wafer from this silicon single crystal, bonding of the donor wafer to a carrier wafer, and reduction of the thickness of the donor wafer, with the result that a silicon layer having a thickness of less than 500 nm bonded to the carrier wafer remains.

대표청구항 ▼

What is claimed is: 1. An SOI wafer comprising a carrier wafer, a monocrystalline silicon layer from a donor wafer, said monocrystalline silicon layer bonded to said carrier wafer, and an insulating layer positioned between the carrier wafer and the monocrystalline silicon layer, wherein the monocr

What is claimed is: 1. An SOI wafer comprising a carrier wafer, a monocrystalline silicon layer from a donor wafer, said monocrystalline silicon layer bonded to said carrier wafer, and an insulating layer positioned between the carrier wafer and the monocrystalline silicon layer, wherein the monocrystalline silicon layer has a thickness of less than 500 nm, an excess of interstitial silicon atoms prevailing in the entire volume of the monocrystalline silicon layer, and agglomerated interstitial silicon atoms present in at least a partial region of the silicon layer. 2. The SOI wafer of claim 1, the silicon layer of which has an oxygen content of 3��1017/cm3 to 7��1017/cm3. 3. The SOI wafer of claim 2, wherein a silicon oxide layer is situated between the silicon layer and the carrier wafer, said silicon oxide layer having a layer thickness homogeneity of less than 1% given a thickness in the range of 3 nm to 30 nm or a layer thickness homogeneity of less than 2% given a thickness in the range of 1 nm to less than 3 nm. 4. The SOI wafer of claim 2, the silicon layer of which has an oxygen content of 5��1017/cm3 to 7��1017/cm3. 5. The SOI wafer of claim 4, the silicon layer of which has an oxygen content of 5��1017/cm3 to 6��1017/cm3. 6. The SOI wafer of claim 4, wherein a silicon oxide layer is situated between the silicon layer and the carrier wafer, said silicon oxide layer having a layer thickness homogeneity of less than 1% given a thickness in the range of 3 nm to 30 nm or a layer thickness homogeneity of less than 2% given a thickness in the range of 1 nm to less than 3 nm. 7. The SOI wafer of claim 1, wherein a silicon oxide layer is situated between the silicon layer and the carrier wafer, said silicon oxide layer having a layer thickness homogeneity of less than 1% given a thickness in the range of 3 nm to 30 nm or a layer thickness homogeneity of less than 2% given a thickness in the range of 1 nm to less than 3 nm. 8. The SOI wafer of claim 1, wherein the density of agglomerated interstitial silicon atoms is less than 104/cm3. 9. The SOI wafer of claim 1, wherein the thickness of the monocrystalline silicon layer is about 100 nm. 10. The SOI wafer of claim 1, wherein the monocrystalline silicon layer is free of large dislocation loops.