A method of forming a semiconductor on glass structure includes: establishing an exfoliation layer on a semiconductor wafer; contacting the exfoliation layer of the semiconductor wafer to a glass substrate; applying pressure, temperature and voltage to the semiconductor wafer and the glass substrate
A method of forming a semiconductor on glass structure includes: establishing an exfoliation layer on a semiconductor wafer; contacting the exfoliation layer of the semiconductor wafer to a glass substrate; applying pressure, temperature and voltage to the semiconductor wafer and the glass substrate, without a vacuum atmosphere, such that a bond is established therebetween via electrolysis; and applying stress such that the exfoliation layer separates from the semiconductor wafer and remains bonded to the glass substrate.
대표청구항▼
The invention claimed is: 1. A method of forming a semiconductor on glass structure, comprising: establishing an exfoliation layer on a semiconductor wafer; contacting the exfoliation layer of the semiconductor wafer to a glass substrate; applying pressure, temperature and voltage to the semiconduc
The invention claimed is: 1. A method of forming a semiconductor on glass structure, comprising: establishing an exfoliation layer on a semiconductor wafer; contacting the exfoliation layer of the semiconductor wafer to a glass substrate; applying pressure, temperature and voltage to the semiconductor wafer and the glass substrate, without a vacuum atmosphere, such that a bond is established therebetween via electrolysis; and applying stress such that: (i) the exfoliation layer separates from the semiconductor wafer and remains bonded to the glass substrate; (ii) the exfoliation layer includes a layer of enhanced oxygen content; and (iii) the glass substrate includes a first substrate layer adjacent the layer of enhanced oxygen content and having a reduced positive ion concentration in which substantially no modifier positive ions are present, and a second substrate layer adjacent the first substrate layer and having an enhanced positive ion concentration of modifier positive ions, including at least one alkaline earth modifier ion. 2. The method of claim 1, wherein the bonding step is carried out in ambient air. 3. The method of claim 1, wherein the bonding step is carried out in a substantially inert gas atmosphere. 4. The method of claim 3, wherein the inert gas is nitrogen. 5. The method of claim 3, wherein the inert gas is argon. 6. The method of claim 3, wherein the inert gas is selected from the group consisting of helium, neon, krypton, xenon and radon. 7. The method of claim 1, wherein the step of establishing the exfoliation layer on the semiconductor wafer includes producing a region of imperfections in a crystal structure of the semiconductor wafer below a contact surface thereof. 8. The method of claim 7, wherein the step of producing a region of imperfections includes using ion implantation to create imperfections between the semiconductor wafer and the exfoliation layer. 9. The method of claim 1, wherein the step of applying temperature to the semiconductor wafer and the glass substrate includes directly or indirectly contacting at least one heated platen to at least one of the semiconductor wafer and the glass substrate. 10. The method of claim 9, further comprising: directly or indirectly contacting at least one heated platen to the semiconductor wafer such that a first temperature is achieved; and directly or indirectly contacting at least one heated platen to the glass substrate such that a second temperature is achieved. 11. The method of claim 10, wherein the first temperature is below the second temperature. 12. The method of claim 9, wherein the temperature of the glass substrate and the semiconductor wafer are elevated to within about +/-300 degrees C. of the strain point of the glass substrate. 13. The method of claim 1, wherein the semiconductor wafer is taken from the group consisting of: silicon (Si), germanium-doped silicon (SiGe), silicon carbide (SiC), germanium (Ge), gallium arsenide (GaAs), GaP, and InP. 14. A method of forming a semiconductor on glass structure, comprising: establishing an exfoliation layer on a semiconductor wafer; contacting the exfoliation layer of the semiconductor wafer to a glass substrate; directly or indirectly contacting at least one heated platen to at least one of the semiconductor wafer and the glass substrate to elevate the temperatures thereof; applying pressure and voltage to the semiconductor wafer and the glass substrate such that a bond is established therebetween via electrolysis; and applying stress such that: (i) the exfoliation layer separates from the semiconductor wafer and remains bonded to the glass substrate; (ii) the exfoliation layer includes a layer of enhanced oxygen content; and (iii) the glass substrate includes a first substrate layer adjacent the layer of enhanced oxygen content and having a reduced positive ion concentration in which substantially no modifier positive ions are present, and a second substrate layer adjacent the first substrate layer and having an enhanced positive ion concentration of modifier positive ions, including at least one alkaline earth modifier ion. 15. The method of claim 14, further comprising: directly or indirectly contacting at least one heated platen to the semiconductor wafer such that a first temperature is achieved; and directly or indirectly contacting at least one heated platen to the glass substrate such that a second temperature is achieved. 16. The method of claim 15, wherein the first temperature is below the second temperature. 17. The method of claim 14, wherein the stress is induced by cooling the bonded glass substrate, exfoliation layer, and semiconductor wafer such that a fracture occurs substantially at a junction of the exfoliation layer and the semiconductor wafer. 18. The method of claim 14, wherein the semiconductor wafer is taken from the group consisting of: silicon (Si), germanium-doped silicon (SiGe), silicon carbide (SiC), germanium (Ge), gallium arsenide (GaAs), GaP, and InP.
연구과제 타임라인
LOADING...
LOADING...
LOADING...
LOADING...
LOADING...
이 특허에 인용된 특허 (22)
Fitzgerald Eugene A., Controlling threading dislocation densities in Ge on Si using graded GeSi layers and planarization.
Brasen Daniel (Lake Hiawatha NJ) Fitzgerald ; Jr. Eugene A. (Bridgewater NJ) Green Martin L. (New Providence NJ) Monroe Donald P. (Berkeley Heights NJ) Silverman Paul J. (Millburn NJ) Xie Ya-Hong (Fl, Semiconductor heterostructure devices with strained semiconductor layers.
※ AI-Helper는 부적절한 답변을 할 수 있습니다.