Device for adjusting at least one parameter, in particular for an aircraft automatic pilot system
원문보기
IPC분류정보
국가/구분
United States(US) Patent
등록
국제특허분류(IPC7판)
G01C-023/00
출원번호
US-0846600
(2004-05-17)
등록번호
US-7400949
(2008-07-15)
우선권정보
FR-03 05948(2003-05-19)
발명자
/ 주소
Granger,St��phane
Bourret,Thierry
출원인 / 주소
Airbus France
대리인 / 주소
Dickinson Wright, PLLC
인용정보
피인용 횟수 :
0인용 특허 :
14
초록▼
A device for adjusting a parameter includes a selector that is actuated by an operator. A coder is driven in rotation by the actuation of the selector and emits a signal representative of the rotation. A first detector detects an actuation of the selector, and a second detector detects the emission
A device for adjusting a parameter includes a selector that is actuated by an operator. A coder is driven in rotation by the actuation of the selector and emits a signal representative of the rotation. A first detector detects an actuation of the selector, and a second detector detects the emission of the signal indicating the change of the selected value. A comparitor, linked to the first and second detectors, determines a malfunction when only one of the first and second detectors makes a detection.
대표청구항▼
The invention claimed is: 1. A device for adjusting at least one parameter, the device comprising: at least one selector which is capable of being actuated by an operator; at least one coder which is driven in rotation by said selector when the latter is actuated, and which then emits a signal repr
The invention claimed is: 1. A device for adjusting at least one parameter, the device comprising: at least one selector which is capable of being actuated by an operator; at least one coder which is driven in rotation by said selector when the latter is actuated, and which then emits a signal representative of that rotation; and at least one arithmetic unit which receives the signal emitted by the coder, formats it, makes a computation to deduce the a selected value therefrom and is capable of transmitting the selected value thus computed, wherein it also comprises: a first detection means which is capable of detecting an actuation of said selector; a second detection means which is capable of detecting the emission of a signal indicating a change of the selected value; and a first comparison means which is linked to said first and second detection means and which deduces a first signal change detection malfunction from the information received from said first and second detection means when only one of said first and second detection means has made a detection. 2. The device as claimed in claim 1, wherein said first comparison means deduces said first malfunction only when said second detection means has detected said change of the selected value while said first detection means has not detected actuation of said selector. 3. The device as claimed in claim 1, wherein it also comprises a first means which prevents the arithmetic unit from transmitting said change of the selected value, on detection of said first malfunction by said first comparison means. 4. The device as claimed in claim 1, wherein it also comprises a second means which emits an alarm signal, on detection of said first malfunction by said first comparison means. 5. The device as claimed in claim 1, wherein it also comprises a display means which is intended to display the selected value, transmitted by said arithmetic unit. 6. The device as claimed in claim 1, wherein said first detection means comprises an auxiliary coder which is mounted in series between said selector and said coder. 7. The device as claimed in claim 1, wherein said second detection means comprises an electronic circuit board which receives the information emitted at the output of said arithmetic unit. 8. The device as claimed in claim 1, wherein it also comprises a third means which is capable of sending an order to change the selected value directly to said arithmetic unit and wherein said first detection means is capable of detecting said order and of indicating the detection of said order to said first comparison means. 9. The device as claimed in claim 1, wherein said arithmetic unit comprises a first computer which receives the signal emitted by the coder and which formats it, and a second computer which receives the signal formatted by said first computer, which makes a computation to deduce the selected value therefrom and which is capable of transmitting the selected value thus computed, and wherein said second detection means is capable of detecting the signal which is formatted by said first computer and which is transmitted by the latter to said second computer. 10. The device as claimed in claim 9, wherein said second detection means and said first comparison means are integrated into said second computer. 11. The device as claimed in claim 9, wherein it also comprises a fourth means which prevents said second computer from registering information transmitted by said first computer, relating to said change of the selected value, when said first comparison means has detected said first malfunction. 12. The device as claimed in claim 11, wherein said fourth means is integrated into said second computer. 13. The device as claimed in claim 9, wherein the link between said first detection means and said first comparison means passes through said first computer and is furnished with a discrete signal processing unit, which is independent of the software functions of said first computer. 14. The device as claimed in claim 1, further comprising: a third detection means for detecting the emission of the signal indicating the change of the selected value; a second comparison means, linked to the first and third detection means, for deducing a second signal change detection malfunction when only one of the first and third detection means makes a detection; and a registration priority means, wherein: the arithmetic unit comprises first and second redundant computing channels, the second detection means and first comparison means are associated with the first computing channel, the third detection means and the second comparison means are associated with the second computing channel, and the registration priority means registers information received from the first computing channel when the second comparison means detects the second malfunction and registers information received from the second computing channel when the first comparison means detects the first malfunction. 15. An aircraft automatic pilot system comprising a control module having a functional unit and the device of claim 1 for adjusting parameters used by the functional unit.
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