초록 ▼

A variable speed data processor includes a clock generator generating a plurality of clocks at different clock rates. Clock select circuitry synchronously selects one of the clocks as an output clock signal to data processing circuitry, based on a data activity indication. Activity logic generates

A variable speed data processor includes a clock generator generating a plurality of clocks at different clock rates. Clock select circuitry synchronously selects one of the clocks as an output clock signal to data processing circuitry, based on a data activity indication. Activity logic generates the data activity indication based at least in part on the existence of data processing activity targeted to the data processing circuitry. When the data processing circuitry experiences bursty data processing activity, the clock rate can shift rapidly between the multiple clock rates, conserving power without substantially diminishing the availability of the data processing circuitry.

대표청구항 ▼

What is claimed is: 1. A graphics data processor comprising: a clock generator to simultaneously generate a plurality of reference clock signals at different clock rates; first clock select circuitry to synchronously select one of the reference clock signals as an output clock signal, the clock sel

What is claimed is: 1. A graphics data processor comprising: a clock generator to simultaneously generate a plurality of reference clock signals at different clock rates; first clock select circuitry to synchronously select one of the reference clock signals as an output clock signal, the clock select circuitry selecting one of the reference clock signals based on a data activity indication; a graphics processing engine operable based on the output clock signal; and first activity logic to detect bus transactions to be directed to the graphics processing engine and to generate the data activity indication based at least in part on the existence of graphics processing activity targeted to the graphics processing engine; wherein the data graphics processing engine is a three-dimensional graphics engine, and wherein the data activity indication is further based on one or more graphics parameters. 2. The graphics data processor of claim 1, wherein the plurality of reference clock signals comprises two clocks. 3. The graphics data processor of claim 2, wherein the clock rates of the two clocks are related by an integer multiple. 4. The graphics data processor of claim 1, wherein the activity logic comprises logic to detect, from among a set of bus transactions including bus transactions targeting the graphics processing engine and bus transactions that do not target the graphics processing engine, the bus transactions targeting the graphics processing engine, and generating the data activity indication when bus transactions targeting the graphics processing engine are detected. 5. The graphics data processor of claim 4, wherein the graphics processingengine is a three-dimensional (3D) graphics processing engine. 6. The graphics data processor of claim 5, further comprising: a two-dimensional graphics processing engine operable based on a single reference clock. 7. The graphics data processor of claim 1, wherein the activity logic comprises logic to detect when the data processing circuitry is actively processing data. 8. The graphics data processor of claim 7, wherein the data activity indication comprises at least two levels indicating different levels of non-zero data processing activity, one of the two indication levels requiring a higher clock rate than the other. 9. The graphics data processor of claim 8, further comprising: second clock select circuitry to synchronously select one of the reference clock signals as a second output clock signal, the second clock select circuitry selecting one of the reference clock signals based on a second data activity indication; a data processing circuitry operable based on the second output clock signal; and second activity logic to generate the second data activity indication based at least in part on the existence of data processing activity targeted to the second data processing circuitry. 10. The graphics data processor of claim 9, wherein the graphics processing engine readies data for the data processing circuitry, the second activity logic generating the second data activity indication when the graphics processing engine readies data for the data processing circuitry. 11. The graphics data processor of claim 1, further comprising: a second data processing circuitry operable operably based on a non-selectable one of the reference clock signals. 12. The graphics data processor of claim 1, wherein the one or more graphics parameters are selected from a group of parameters consisting of parameters related to: a number of active polygons, a frame rate, a graphics image size, and a shading method. 13. An information handling system comprising: a data bus; and a graphics data processor having a clock generator to simultaneously generate a plurality of reference clock signals at different clock rates, an internal dynamic clock controller to synchronously select one of the reference clock signals, data processing circuitry operable based on the selected reference clock signal, and activity logic to signal the dynamic clock controller based at least in part on the existence of data bus activity targeted to the data processing circuitry; wherein the data processing circuitry is a three-dimensional (3D) graphics processing engine, the data processor further comprising a two-dimensional (2D) graphics processing engine, and wherein the activity logic differentiates between data bus activity targeted to the 2D and 3D graphics processing engines. 14. The information handling system of claim 13, wherein the 2D graphics processing engine is operable based on a single reference clock. 15. The information handling system of claim 13, wherein the graphics data processor is a packet processor. 16. A method of operating a graphics data processor, the method comprising: simultaneously generating a plurality of reference clock signals at different clock rates; analyzing whether data processing activity is targeted to a segment of the data processor; and synchronously selecting one of the reference clock signals to apply to the segment of the graphics data processor based at least in part on whether data processing activity is targeted to the segment of the graphics data processor; wherein the segment of the data processor is a three-dimensional (3D) graphics processing engine, wherein analyzing whether data processing activity is targeted to a segment of the graphics data processor comprises detecting when the 3D graphics processing engine is actively processing 3D graphics data. 17. The method of claim 16, further comprising: generating the reference clock signals by dividing a master clock signal by different values. 18. The method of claim 16, further comprising: receiving bus transactions, including bus transactions targeting the segment of the graphics data processor and bus transactions that do not target the segment of the graphics data processor, wherein analyzing comprises detecting bus transactions targeting the segment of the graphics data processor. 19. The method of claim 18, wherein synchronously selecting one of the reference clock signals comprises selecting a reference clock signal at a higher clock rate when bus transactions are targeted to the segment of the graphics data processor than the clock rate of the reference clock signal selected when the segment of the graphics data processor is not processing data. 20. The method of claim 16, wherein selecting one of the reference clock signals further comprising basing the selection of a clock rate on one or more processing parameters set for the 3D graphics processing engine.