Post passivation method for semiconductor chip or wafer
원문보기
IPC분류정보
국가/구분
United States(US) Patent
등록
국제특허분류(IPC7판)
H01L-021/4763
H01L-021/02
출원번호
US-0154662
(2002-05-24)
등록번호
US-7405149
(2008-07-29)
발명자
/ 주소
Lin,Mou Shiung
Lee,Jin Yuan
출원인 / 주소
Megica Corporation
대리인 / 주소
Saile Ackerman LLC
인용정보
피인용 횟수 :
30인용 특허 :
88
초록▼
The present invention adds one or more thick layers of polymer dielectric and one or more layers of thick, wide metal lines on top of a finished semiconductor wafer, post-passivation. The thick, wide metal lines may be used for long signal paths and can also be used for power buses or power planes,
The present invention adds one or more thick layers of polymer dielectric and one or more layers of thick, wide metal lines on top of a finished semiconductor wafer, post-passivation. The thick, wide metal lines may be used for long signal paths and can also be used for power buses or power planes, clock distribution networks, critical signal, and re-distribution of I/O pads for flip chip applications. Photoresist defined electroplating, sputter/etch, or dual and triple damascene techniques are used for forming the metal lines and via fill.
대표청구항▼
What is claimed is: 1. A method for fabricating an integrated circuit chip, comprising: providing a silicon wafer, a transistor in or on said silicon wafer, a metallization structure over said silicon wafer, wherein said metallization structure comprises a first metal layer and a second metal layer
What is claimed is: 1. A method for fabricating an integrated circuit chip, comprising: providing a silicon wafer, a transistor in or on said silicon wafer, a metallization structure over said silicon wafer, wherein said metallization structure comprises a first metal layer and a second metal layer over said first metal layer, a dielectric layer between said first and second metal layers, a contact pad over said silicon wafer, wherein said contact pad has a top surface and a sidewall, wherein said top surface has a first region and a second region between said first region and said sidewall, and a passivation layer over said metallization structure, over said dielectric layer and on said second region, wherein a first opening in said passivation layer is over said first region and exposes said first region, and wherein said passivation layer comprises a nitride; forming a first polymer layer on said passivation layer, wherein a second opening in said first polymer layer is over said first region and exposes said first region, and wherein said first polymer layer has a thickness between 2 and 50 micrometers; forming a third metal layer on said first polymer layer and on said contact pad, wherein said forming said third metal layer comprises sputtering a titanium-containing layer with a thickness between 0.01 and 3 micrometers on said first polymer layer and on said first region, sputtering a seed layer with a thickness between 0.05 and 3 micrometers on said titanium-containing layer, forming a photoresist layer on said seed layer, wherein a third opening in said photoresist layer is over said seed layer and exposes said seed layer, electroplating a gold layer with a thickness between 2 and 100 micrometers on said seed layer exposed by said third opening, removing said photoresist layer, removing said seed layer not under said gold layer, and removing said titanium-containing layer not under said gold layer; and forming a second polymer layer on said third metal layer, on said first polymer layer, and over said silicon wafer, wherein a fourth opening in said second polymer layer is over said third metal layer and exposes said third metal layer. 2. The method of claim 1, wherein the position of said fourth opening from a top perspective view is different from that of said first opening. 3. The method of claim 1, after said forming said second polymer layer, further comprising forming a fourth metal layer connected to said third metal layer through said fourth opening. 4. The method of claim 3, wherein said forming said fourth metal layer comprises sputtering. 5. The method of claim 3, wherein said forming said fourth metal layer comprises electroplating. 6. The method of claim 1, wherein said first polymer layer comprises polyimide. 7. The method of claim 1, wherein said passivation layer further comprises an oxide. 8. The method of claim 1, wherein said nitride comprises oxynitride. 9. A method for fabricating an integrated circuit chip, comprising: providing a silicon wafer, transistor in or on said silicon wafer, a metallization structure over said silicon wafer, wherein said metallization structure comprises a first metal layer and a second metal layer over said first metal layer, a dielectric layer between said first and second metal layers, a contact pad over said silicon wafer, and a passivation layer over said metallization structure and over said dielectric layer, wherein said passivation layer comprises a nitride; forming a first polymer layer on said passivation layer, wherein a first opening in said first polymer layer is over said contact pad and exposes said contact pad, and wherein said first polymer layer has a thickness between 2 and 50 micrometers; forming a third metal layer connected to said contact pad through said first opening, wherein said forming said third metal layer comprises sputtering a titanium-containing layer with a thickness between 0.01 and 3 micrometers, sputtering a seed layer with a thickness between 0.05 and 3 micrometers over said titanium-containing layer, forming a photoresist layer on said seed layer, wherein a second opening in said photoresist layer is over said seed layer and exposes said seed layer, electroplating a gold layer with a thickness between 2 and 100 micrometers on said seed layer exposed by said second opening, removing said photoresist layer, removing said seed layer not under said gold layer, and removing said titanium-containing layer not under said gold layer; and forming a second polymer layer on said third metal layer and over said silicon wafer. 10. The method of claim 9, wherein a third opening in said second polymer layer is over said third metal layer and exposes said third metal layer, wherein the position of said third opening from a top perspective view is different from that of said first opening. 11. The method of claim 9, after said forming said second polymer layer, further comprising forming a fourth metal layer connected to said third metal layer through a third opening in said second polymer layer. 12. The method of claim 11, wherein said forming said fourth metal layer comprises sputtering. 13. The method of claim 11, wherein said forming said fourth metal layer comprises electroplating. 14. The method of claim 9, wherein said forming said third metal layer comprises said forming said third metal layer on said first polymer layer and on said contact pad. 15. The method of claim 9, wherein a third opening in said passivation layer is over said contact pad and exposes said contact pad. 16. The method of claim 9, wherein said first polymer layer comprises polyimide. 17. The method of claim 9, wherein said passivation layer further comprises an oxide. 18. The method of claim 9, wherein said nitride comprises oxynitride. 19. A method for fabricating an integrated circuit chip, comprising: providing a silicon wafer, a transistor in or on said silicon wafer, a metallization structure over said silicon wafer, wherein said metallization structure comprises a first metal layer and a second metal layer over said first metal layer, a dielectric layer between said first and second metal layers, a contact pad over said silicon wafer, and a passivation layer over said metallization structure and over said dielectric layer, wherein a first opening in said passivation layer is over said contact pad and exposes said contact pad, and wherein said passivation layer comprises a nitride; forming a third metal layer over said passivation layer and over said contact pad, wherein said third metal layer is connected to said contact pad through said first opening, wherein said forming said third metal layer comprises sputtering an adhesion layer with a thickness between 0.01 and 3 micrometers, sputtering a seed layer with a thickness between 0.05 and 3 micrometers over said adhesion layer, forming a photoresist layer on said seed layer, wherein a second opening in said photoresist layer is over said seed layer and exposes said seed layer, electroplating a gold layer with a thickness between 2 and 100 micrometers on said seed layer exposed by said second opening, removing said photoresist layer, removing said seed layer not under said gold layer, and removing said adhesion layer not under said gold layer; and forming a first polymer layer on said third metal layer, over said passivation layer, and over said silicon wafer. 20. The method of claim 19, wherein a third opening in said first polymer layer is over said third metal layer and exposes said third metal layer. 21. The method of claim 20, wherein the position of said third opening from a top perspective view is different from that of said first opening. 22. The method of claim 20, after said forming said first polymer layer, further comprising forming a fourth metal layer connected to said third metal layer through said third opening. 23. The method of claim 22, wherein said forming said fourth metal layer comprises sputtering. 24. The method of claim 22, wherein said forming said fourth metal layer comprises electroplating. 25. The method of claim 19 further comprising forming a second polymer layer on said passivation layer, wherein a third opening in said second polymer layer is over said contact pad and exposes said contact pad, followed by said forming said third metal layer further on said second polymer layer. 26. The method of claim 25, wherein said second polymer layer has a thickness between 2 and 50 micrometers. 27. The method of claim 19, wherein said nitride comprises silicon nitride. 28. The method of claim 19, wherein said nitride comprises silicon oxynitride. 29. The method of claim 25, wherein said second polymer layer comprises polyimide. 30. The method of claim 19, wherein said passivation layer further comprises an oxide. 31. The method of claim 19, wherein said nitride comprises oxynitride.
연구과제 타임라인
LOADING...
LOADING...
LOADING...
LOADING...
LOADING...
이 특허에 인용된 특허 (88)
Ichikawa Matsuo,JPX, Bonding pad structures for semiconductor integrated circuits.
Golshan Shahin (Midland TX) St. Martin Craig A. (Midland TX) Rhodine Craig W. (Midland TX), Configuration and method for positioning semiconductor device bond pads using additional process layers.
Chittipeddi Sailesh ; Cochran William T. ; Smooha Yehuda, Device and method of manufacture for an integrated circuit having a BIST circuit and bond pads incorporated therein.
Chittipeddi, Sailesh; Cochran, William Thomas; Smooha, Yehuda, Dual damascene bond pad structure for lowering stress and allowing circuitry under pads.
Efland Taylor R. (Richardson TX) Cotton Dave (Plano TX) Skelton Dale J. (Plano TX), ESD protection structure using LDMOS diodes with thick copper interconnect.
Nakanishi Keiichirou (Kokubunji JPX) Yamada Minoru (Hanno JPX) Saitoh Tatsuya (Kokubunji JPX) Yamamoto Kazumichi (Kokubunji JPX), Integrated circuit device having an ic chip mounted on the wiring substrate and having suitable mutual connections betwe.
Lamson Michael A. (Van Alstyne TX) Edwards Darvin R. (Dallas TX), Integrated circuit device having bumped power supply buses over active surface areas and method of manufacture thereof.
Shen Chi-Cheong ; Abbott Donald C. ; Bucksch Walter,DEX ; Corsi Marco ; Efland Taylor Rice ; Erdeljac John P. ; Hutter Louis Nicholas ; Mai Quang ; Wagensohner Konrad,DEX ; Williams Charles Edward, Integrated circuit with bonding layer over active circuitry.
Bertin Claude L. (South Burlington VT) Howell Wayne J. (South Burlington VT) Hedberg Erik L. (Essex Junction VT) Kalter Howard L. (Colchester VT) Kelley ; Jr. Gordon A. (Essex Junction VT), Integrated memory cube, structure and fabrication.
David V. Horak ; William A. Klaasen ; Thomas L. McDevitt ; Mark P. Murray ; Anthony K. Stamper, Interconnection structure and method for fabricating same.
Farrar Paul A. (South Burlington VT) Geffken Robert M. (Burlington VT) Kroll Charles T. (Raleigh NC), Method for forming dense multilevel interconnection metallurgy for semiconductor devices.
Efland Taylor R. ; Mai Quang X. ; Williams Charles E. ; Keller Stephen A., Method of forming improved thick plated copper interconnect and associated auxiliary metal interconnect.
Bandyopadhyay Basab ; Fulford ; Jr. H. Jim ; Dawson Robert ; Hause Fred N. ; Michael Mark W. ; Brennan William S., Method of making an integrated circuit which uses an etch stop for producing staggered interconnect lines.
Costrini Gregory ; Goldblatt Ronald Dean ; Heidenreich ; III John Edward ; McDevitt Thomas Leddy, Method/structure for creating aluminum wirebound pad on copper BEOL.
Laurent Basteres FR; Ahmed Mhani FR; Fran.cedilla.ois Valentin FR; Jean-Michel Karam FR, Monolithic integrated circuit incorporating an inductive component and process for fabricating such an integrated circuit.
E. Henry Stevens, Process and manufacturing tool architecture for use in the manufacturing of one or more protected metallization structures on a workpiece.
Sun Shih-Wei (Austin TX) Kosa Yasunobu (Austin TX) Yeargain John R. (Austin TX), Process for forming a structure which electrically shields conductors.
Seppala Bryan R. (Apple Valley MN) Backer Todd G. (Apple Valley MN) Maier Lothar (Eden Prairie MN), Process for manufacturing a semiconductor device bump electrode using a rapid thermal anneal.
Toyosawa, Kenji; Ono, Atsushi; Chikawa, Yasunori; Sakaguchi, Nobuhisa; Nakamura, Nakae; Nakata, Yukinori, Semiconductor device having active element connected to an electrode metal pad via a barrier metal layer and interlayer insulating film.
Akagawa Masatoshi,JPX ; Higashi Mitsutoshi,JPX ; Iizuka Hajime,JPX ; Arai Takehiko,JPX, Semiconductor device having an element with circuit pattern thereon.
Wenzel James F. (Austin TX) Chopra Mona A. (Austin TX) Foster Stephen W. (Dripping Springs TX), Semiconductor device having built-in high frequency bypass capacitor.
Ueda Tetsuya,JPX ; Tamaoka Eiji,JPX ; Aoi Nobuo,JPX, Semiconductor device having multilevel interconnection structure and method for fabricating the same.
※ AI-Helper는 부적절한 답변을 할 수 있습니다.