[특허]IC comprising network of microprocessors communicating data messages along asynchronous channel segments using ports including validity and accept signal registers and with split / join capability

IC comprising network of microprocessors communicating data messages along asynchronous channel segments using ports including validity and accept signal registers and with split / join capability 원문보기

IPC분류정보
국가/구분	United States(US) Patent 등록
국제특허분류(IPC7판)	G06F-015/17 G06F-015/16
출원번호	US-0466083 (2006-08-21)
등록번호	US-7406584 (2008-07-29)
발명자 / 주소	Jones,Anthony Mark
출원인 / 주소	Ambric, Inc.
대리인 / 주소	Marger Johnson & McCollom, P.C.
인용정보	피인용 횟수 : 0 인용 특허 : 64

초록 ▼

Embodiments of the invention are directed to a communication network on an integrated circuit for a number of interconnected microprocessors. The network is made from a number of sending nodes and receiving nodes each coupled by a communication channel. Individual communication channels operate at individually controllable clock speeds. Data messages sent between nodes pass at the speed of the communication channels. These data messages are sent by a sending port that includes registers for storing data and registers for protocol signals that control the timing and movement of the data. Data crosses clock boundaries without data loss. At least some of the microprocessors include fork functions that output a data stream to more than one output port. Similarly, at least some of the microprocessors include join functions that can create a single data stream from inputs from more than one input port.

대표청구항 ▼

What is claimed is: 1. An integrated circuit, comprising: a communication network including a plurality of clocked communication channel segments, at least some of the communication channel segments structured to operate at different clock rates; and a plurality of microprocessor pairs each coupled between a single one of the plurality of communication channel segments of the communication network, each of the plurality of microprocessor pairs including microprocessors structured to operate independently from one another and at an independently controllable clock rate, and each microprocessor having: more than one sending port structured to send a split outgoing data message from its associated processor over at least two communication channels of the communication network, each sending port including one or more sequential output registers, each sequential output register including: a data register for storing a data portion of the outgoing data message, a valid register for storing an indication of a validity of the data stored in the data register, and an accept register for storing an indication that a subsequent element in the communication network is able to accept one of the outgoing data messages, and more than one receiving port structured to receive incoming data messages for its associated processor from the communication network, each receiving port including one or more sequential input registers, each sequential input register including: a data register for storing a data portion of the incoming messages, a valid register for storing an indication of a validity of the data stored in the data register, and an accept register for storing an indication that the sequential input register is able to accept one of the incoming data messages. 2. An integrated circuit according to claim 1 in which a clock rate of any of the plurality of microprocessors is independent of a clock rate of any of the plurality of communication channel segments in the communication network. 3. An integrated circuit according to claim 1 in which the at least one sending port is structured to retain the data message indefinitely until it receives the second protocol signal. 4. An integrated circuit according to claim 1 in which the one or more sequential output registers includes a packet register for storing an indication of whether the data stored in the data register is a member of a particular packet. 5. An integrated circuit according to claim 1 in which all of the at least two communication channels transport a portion of the split outgoing data message. 6. An integrated circuit according to claim 1 in which at least one of the incoming data messages comprises a processing instruction. 7. An integrated circuit according to claim 1 in which each sending port is structured to send the outgoing data message to a selected receiving port at any time that the selected receiving port is able to receive the outgoing data message. 8. An integrated circuit according to claim 1 in which each of the sending ports in the integrated circuit has approximately similar electrical loading characteristics. 9. An integrated circuit according to claim 1 in which each of the receiving ports in the integrated circuit has approximately similar electrical loading characteristics. 10. An integrated circuit according to claim 1 in which the split outgoing data message comprises a first full outgoing data message on a first of the at least two communication channels and a second full data message on a second of the at least two communication channels. 11. An integrated circuit according to claim 10 in which the first full data outgoing message and second full data message are identical. 12. An integrated circuit, comprising: a communication network including a plurality of separate components, each component structured to carry data at controllable clock rates; and a plurality of processors coupled to the communication network, each of the processors structured to operate based on information only within each processor and each of the processors structured to generate messages, each of the processors having: at least two sending ports structured to send an outgoing data message from its associated processor over the communication network aligned to one of the clock intervals of the communication network, each sending port including one or more sequential output registers, each sequential output register including: a data register for storing a data portion of the outgoing data message, a valid register for storing an indication of a validity of the data stored in the data register, and an accept register for storing an indication that a next processor connected over the communication network can accept the data message; and at least two receiving ports structured to receive a split incoming data message for its associated processor from at least two components of the communication network, each receiving port including one or more sequential input registers, each sequential input register including: a data register for storing a data portion of the incoming data message, a valid register for storing an indication of a validity of the data stored in the data register, and an accept register for storing an indication that a next object in the communication network can accept a portion of the split incoming data message. 13. An integrated circuit according to claim 12 in which any of the plurality of processors is structured to send data messages to any other of the plurality of processors through the communication network. 14. An integrated circuit according to claim 12 in which any of the plurality of processors is structured to send data messages to itself. 15. An integrated circuit according to claim 12 in which each sending port is structured to retain the data message indefinitely until one of the receiving ports sends a signal to the sending port that indicates the data message will be accepted and removed from the communication network. 16. An integrated circuit according to claim 12 in which one or more sequential output registers includes a packet register for storing an indication of whether the data stored in the data register is a member of a particular packet. 17. An integrated circuit according to claim 12 in which each of the plurality of processors is structured to generate messages at any time relative to each other processor. 18. An integrated circuit according to claim 12 in which each of the processors is structured to generate outgoing messages at any time relative to the clock rate of the communication network. 19. An integrated circuit according to claim 18 in which a generated outgoing data message is transmitted by the communication network at a next subsequent clock signal of the communication network after receiving the outgoing generated data message from the sending port. 20. An integrated circuit according to claim 12 in which each of the processors operates according to an independently controlled clock signal. 21. An integrated circuit according to claim 20 in which the clock signal for a first of the plurality of processors has a different frequency than the clock signal for a second of the plurality of processors. 22. An integrated circuit according to claim 20 in which a frequency of the clock signal for any of the processors is different from a frequency of a communication network clock. 23. An integrated circuit according to claim 12 in which all of the at least two components of the communication network transport a portion of the split incoming data message. 24. An integrated circuit according to claim 12 in which the incoming data message is interleaved across the at least two components of the communication network. 25. An integrated circuit according to claim 12 in which a first portion of the incoming data message is transmitted across a first of the at least two components of the communication network and in which a second portion of the incoming data message is transmitted across a second of the at least two components of the communication network.

이 특허에 인용된 특허 (64)

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Songer, Christopher Mark; Konas, Pavlos; Gauthier, Marc E.; Chea, Kevin C., Abstraction of configurable processor functionality for operating systems portability.
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Master, Paul L.; Hogenauer, Eugene; Scheuermann, Walter James, Adaptive integrated circuitry with heterogeneous and reconfigurable matrices of diverse and adaptive computational units having fixed, application specific computational elements.
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Kurtze Jeffrey D. ; Frink Craig R. ; Hamilton James ; Sarnowski Frank C. ; Cacciatore Raymond D. ; Markinson Scott A. ; Lamenza Michael F. ; O'Connor Anthony ; Eshraghian Hamed, Apparatus and method for controlling transfer of data between and processing of data by interconnected data processing elements.
상세보기
Earl A. Killian ; Ricardo E. Gonzalez ; Ashish B. Dixit ; Monica Lam ; Walter D. Lichtenstein ; Christopher Rowen ; John C. Ruttenberg ; Robert P. Wilson ; Albert Ren-Rui Wang ; Dror Eliezer, Automated processor generation system for designing a configurable processor and method for the same.
상세보기
Phillips Christopher E. ; Wong Dale ; Pfalzer Karl W., Behavioral silicon construct architecture and mapping.
상세보기
Chappel John F.,CAX ; Tresidder Michael J.,CAX, Bi-directional asynchronous transfer scheme using a single handshake.
상세보기
Chrysanthos Nicholas Dellarocas ; Thomas W. Malone, COMPUTER SYSTEM AND COMPUTER IMPLEMENTED PROCESS FOR REPRESENTING SOFTWARE SYSTEM DESCRIPTIONS AND FOR GENERATING EXECUTABLE COMPUTER PROGRAMS AND COMPUTER SYSTEM CONFIGURATIONS FROM SOFTWARE SYSTEM .
상세보기
Brian C. Faith ; Thomas Oelsner GB; Gary N. Lai, Configurable computational unit embedded in a programmable device.
상세보기
Steven Paul Winegarden ; Bart Reynolds ; Brian Fox ; Jean-Didier Allegrucci ; Sridhar Krishnamurthy ; Danesh Tavana ; Arye Ziklik ; Andreas Papaliolios ; Stanley S. Yang ; Fung Fung Lee, Configurable processor system unit.
상세보기
Jones, Andrew M.; Carey, John A.; Hasegawa, Atsushi, Connection ports for interconnecting modules in an integrated circuit.
상세보기
Dellinger Eric F. ; Hwang L. James ; Mitra Sujoy ; Mohan Sundararajarao ; Wittig Ralph D., Context-sensitive self implementing modules.
상세보기
Cismas Sorin C., Data flow integrated circuit architecture.
상세보기
Adrian Philip Wise GB; Martin William Sotheran GB; William Philip Robbins GB, Data pipeline system and data encoding method.
상세보기
Wise Adrian Philip,GBX ; Robbins William Philip,GBX ; Sotheran Martin William,GBX, Data pipeline system and data encoding method.
상세보기
Terada Hiroaki (Osaka JPX) Asada Katsuhiko (Hyogo JPX) Nishikawa Hiroaki (Osaka JPX) Shima Kenji (Hyogo JPX) Komori Shinji (Hyogo JPX) Meichi Mitsuo (Hyogo JPX) Shimizu Masahisa (Osaka JPX) Miyata So, Data transmission apparatus having cascaded data processing modules for daisy chain data transfer.
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Schaumont, Patrick; Vernalde, Serge; Cockx, Johan, Design apparatus and a method for generating an implementable description of a digital system.
상세보기
Rompaey Karl Van,BEX ; Verkest Diederik,BEX ; Vanhoof Jan,BEX ; Lin Bill,BEX ; Bolsens Ivo,BEX ; De Man Hugo,BEX, Design environment and a design method for hardware/software co-design.
상세보기
Schaumont Patrick,BEX ; Vernalde Serge,BEX ; Cockx Johan,BEX, Design environment and a method for generating an implementable description of a digital system.
상세보기
Rupp, Charle' R.; Garverick, Timothy L.; Arnold, Jeffrey, Design methodology for merging programmable logic into a custom IC.
상세보기
Jones,Anthony Mark, Development system for an integrated circuit having standardized hardware objects.
상세보기
Mithal, Arvind; Hoe, James C., Digital circuit synthesis system.
상세보기
Snyder, Warren, Digital configurable macro architecture.
상세보기
Clawson James, Distributed computing architecture.
상세보기
Loghmani Masoud ; Davis Steven ; Bolon Brian, Distributed predictive and event-driven processing environment.
상세보기
Roussakov Vladimir P.,RUX, Dynamically reconfigurable distributed integrated circuit processor and method.
상세보기
Poff Thomas C. ; Minami John Shigeto ; Koyama Ryo, Hardware accelerator for an object-oriented programming language.
상세보기
Dave Bharat P. ; Jha Niraj K., Hardware-software co-synthesis of hierarchical heterogeneous distributed embedded systems.
상세보기
Sihlbom, Bjorn; Stollon, Neal S.; McCaughey, Thomas, Heterogeneous integrated circuit with reconfigurable logic cores.
상세보기
Kommrusch, Steve, High speed asynchronous bus for an integrated circuit.
상세보기
Seidel, Eiko; Wiebke, Thomas, Hybrid ARQ method for packet data transmission.
상세보기
Gilson, Kent L., Hypercomputer.
상세보기
Osann ; Jr. Robert, Integrated circuit architecture having an array of test cells providing full controllability for automatic circuit verification.
상세보기
Fibranz, Heiko; Plaettner, Eckehard, Integrated circuit having a synchronous and an asynchronous circuit and method for operating such an integrated circuit.
상세보기
Baldwin David Robert,GBX, Integrated graphics subsystem with message-passing architecture.
상세보기
Chelcea, Tiberiu; Nowick, Steven M., Low latency FIFO circuits for mixed asynchronous and synchronous systems.
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Trimberger, Stephen M., Method and apparatus for protecting proprietary configuration data for programmable logic devices.
상세보기
Parks Jay Scott ; Jacobs Christopher William, Method and system for data translation.
상세보기
Wu Kevin (San Jose CA), Method and system for updating derived items in a view model which includes multiple coordinate systems.
상세보기
Jain Prem P., Method for graphically representing a digital device as a behavioral description with data and control flow elements, and for converting the behavioral description to a structural description.
상세보기
Cary Ussery ; Oz Levia ; Raymond Ryan, Method of generating application specific integrated circuits using a programmable hardware architecture.
상세보기
Ussery Cary ; Levia Oz ; Ryan Raymond, Method of generating application specific integrated circuits using a programmable hardware architecture.
상세보기
Miller, Ian D.; Edwards, Stephen G.; Harris, Jonathan C.; Jensen, James E.; Kollegger, Andreas B.; Schanck, Christopher R. S.; Wu, Conor C., Method of transforming software language constructs to functional hardware equivalents.
상세보기
Barry, Edwin F.; Pechanek, Gerald G.; Drabenstott, Thomas L.; Wolff, Edward A.; Pitsianis, Nikos P.; Morris, Grayson, Methods and apparatus for ManArray PE-PE switch control.
상세보기
Barry, Edwin F.; Drabenstott, Thomas L.; Pechanek, Gerald G.; Pitsianis, Nikos P., Methods and apparatus for manifold array processing.
상세보기
Revilla, Juan Guillermo; Barry, Edwin F.; Marchand, Patrick Rene; Pechanek, Gerald G., Methods and apparatus to dynamically reconfigure the instruction pipeline of an indirect very long instruction word scalable processor.
상세보기
Jones, Andrew M.; Barnes, William B., Monitoring error conditions in an integrated circuit.
상세보기
Rupp, Charle' R., Multi-scale programmable array.
상세보기
Cismas, Sorin C., Multithreaded data/context flow processing architecture.
상세보기
Wise Adrian Philip,GBX, Pipeline processing machine having a plurality of reconfigurable processing stages interconnected by a two-wire interface bus.
상세보기
Wise Adrian P.,GBX ; Sotheran Martin W.,GBX ; Robbins William P.,GBX, Pipeline processing machine with interactive stages operable in response to tokens and system and methods relating thereto.
상세보기
Sato, Tomoyoshi, Program product and data processor.
상세보기
Schreiber, Robert S.; Rau, B. Ramakrishna; Gupta, Shail Aditya; Kathail, Vinod K.; Anik, Sadun, Programmatic synthesis of processor element arrays.
상세보기
Felix G. T. I. Andrew ; David A. Sobeski, Property linking in object-oriented computing environments.
상세보기
Douady Cesar,FRX, Protocol and bus link system between components of a micro-controller.
상세보기
Alan David Marshall GB; Anthony Stansfield GB; Jean Vuillemin FR, Reconfigurable processor devices.
상세보기
Marshall, Alan David; Stansfield, Anthony; Vuillemin, Jean, Reconfigurable processor devices.
상세보기
Vaidyanathan,Krishnamurthy; Birru,Dagnachew, Reprogrammable apparatus supporting the processing of a digital signal stream and method.
상세보기
Atkinson, Kevin E.; Dwyer, Timothy H.; Johnson, Ryan C.; Elpers, Mark D.; Helgemo, Dirk R., Silicon object array with unidirectional segmented bus architecture.
상세보기
Rostoker Michael D. ; Watkins Daniel R., System and method for creating and validating structural description of electronic system from higher-level and behavior.
상세보기
Wilson, Robert P.; Maydan, Dror E.; Wang, Albert Ren-Rui; Lichtenstein, Walter D.; Tjiang, Weng Kiang, System and method for dynamically designing and evaluating configurable processor instructions.
상세보기
Davis Donald J. ; Bennett Toby D. ; Harris Jonathan C. ; Miller Ian D. ; Edwards Stephen G., System and method for programming the hardware of field programmable gate arrays (FPGAs) and related reconfiguration resources as if they were software by creating hardware objects.
상세보기
Masteller Steven Robert, System for facilitating interfacing between multiple non-synchronous systems utilizing an asynchronous FIFO that uses asynchronous logic.
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Morad, Amir; Yavits, Leonid, Video encoding device.
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IPC	Description
A	생활필수품
A62	인명구조; 소방(사다리 E06C)
A62B	인명구조용의 기구, 장치 또는 방법(특히 의료용에 사용되는 밸브 A61M 39/00; 특히 물에서 쓰이는 인명구조 장치 또는 방법 B63C 9/00; 잠수장비 B63C 11/00; 특히 항공기에 쓰는 것, 예. 낙하산, 투출좌석 B64D; 특히 광산에서 쓰이는 구조장치 E21F 11/00)
A62B-1/08	.. 윈치 또는 풀리에 제동기구가 있는 것

내보내기 구분	파일저장 인쇄 메일전송
구성항목	기본정보 상세정보 관리번호, 국가코드, 자료구분, 상태, 출원번호, 출원일자, 공개번호, 공개일자, 등록번호, 등록일자, 발명명칭(한글), 발명명칭(영문), 출원인(한글), 출원인(영문), 출원인코드, 대표IPC 관리번호, 국가코드, 자료구분, 상태, 출원번호, 출원일자, 공개번호, 공개일자, 공고번호, 공고일자, 등록번호, 등록일자, 발명명칭(한글), 발명명칭(영문), 출원인(한글), 출원인(영문), 출원인코드, 대표출원인, 출원인국적, 출원인주소, 발명자, 발명자E, 발명자코드, 발명자주소, 발명자 우편번호, 발명자국적, 대표IPC, IPC코드, 요약, 미국특허분류, 대리인주소, 대리인코드, 대리인(한글), 대리인(영문), 국제공개일자, 국제공개번호, 국제출원일자, 국제출원번호, 우선권, 우선권주장일, 우선권국가, 우선권출원번호, 원출원일자, 원출원번호, 지정국, Citing Patents, Cited Patents
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연합인증

IC comprising network of microprocessors communicating data messages along asynchronous channel segments using ports including validity and accept signal registers and with split / join capability 원문보기

초록 ▼

대표청구항 ▼

연구과제 타임라인

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연합인증

IC comprising network of microprocessors communicating data messages along asynchronous channel segments using ports including validity and accept signal registers and with split / join capability 원문보기

초록 ▼

대표청구항 ▼

연구과제 타임라인

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