[특허]Circuit arrangement having a power transistor and a drive circuit for the power transistor

Infineon Technologies AG

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특허 상세정보

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Circuit arrangement having a power transistor and a drive circuit for the power transistor

특허상세정보
국가/구분	United States(US) Patent 등록
국제특허분류(IPC7판)	H03K-017/687
미국특허분류(USC)	327/427; 327/437
출원번호	US-0109318 (2005-04-19)
등록번호	US-7408398 (2008-08-05)
우선권정보	DE-10 2004 018 823(2004-04-19)
발명자 / 주소	Sander,Rainald
출원인 / 주소	Infineon Technologies AG
대리인 / 주소	Maginot, Moore & Beck
인용정보	피인용 횟수 : 10 인용 특허 : 13

초록
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Circuit arrangement having a power transistor and a drive circuit for the power transistor The invention relates to a circuit arrangement having the following features: a power transistor (T) having a control terminal (G) and also a first and second load path terminal (D, S), the first load path terminal (D) of which is connected to a terminal for supply potential (V1) via an inductance-exhibiting line terminal (1) and the second load path terminal (S) of which serves for connecting a load (Z), and a first drive unit (10) for off-state driving of the power transistor (T) having an output (11) connected to the control terminal (G) of the power transistor (T1), and having a first current source arrangement (Iq1) connected between the output (AK) and a first drive potential (GND), in which case the first drive unit has a second current source arrangement (S2off, Iq2; S2off, Iq2, Iq21), which is connected to the output (AK) and which provides a current (I2; I2, I21) that is dependent on a temporal change in a terminal potential (Vd) at the first load path terminal (D) of the power transistor (T).

대표
청구항
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The invention claimed is: 1. A circuit arrangement comprising: a power transistor having a control terminal and first and second load path terminals, the first load path terminal being connected to a terminal for supply potential via an inductance-exhibiting line and the second load path terminal configured to be connected to a load, and a first drive unit having an output connected to the control terminal of the power transistor and configured to drive the power transistor in an off-state, the first drive unit having a first current source arrangement connected between the output and a first drive potential, the first drive unit further having a second current source arrangement connected to the output, the second current source arrangement configured to provide a first current that is dependent on an upward integration of a temporal change in a terminal potential at the first load path terminal starting from a time in which a rise in the terminal potential is produced on the inductance-exibiting line. 2. The circuit arrangement as claimed in claim 1, wherein the second current source arrangement is further configured to provide the first current such that the first current is dependent on an upward integration of the temporal change in the terminal potential starting from the time in which the rise in the terminal potential is produced on the inductance-exhibiting line, up to a time at which the load terminal potential reaches a maximum value. 3. The circuit arrangement as claimed in claim 1, wherein the second current source arrangement is connected between the control terminal and a second supply potential. 4. The circuit arrangement as claimed in claim 1, wherein the second current source arrangement is further configured to provide the first current such that the first current is also dependent on a load voltage. 5. The circuit arrangement as claimed in claim 4, the second current source arrangement is further configured to provide the first current such that the first current is related to said load voltage via a nonlinear characteristic curve. 6. The circuit arrangement as claimed in claim 4, wherein the second current source arrangement comprises a first current source configured to provide a first current component dependent on the change in the terminal potential, and a second current source configured to provide a second current component dependent on the load voltage, the first current including the first current component and the second current component. 7. The circuit arrangement as claimed in claim 3, wherein the second current source arrangement includes a depletion transistor having a load path, a control terminal and a substrate terminal, the load path of the depletion transistor being connected between the second supply potential and the output terminal, the control terminal of the depletion resistor configured to receive a first drive signal dependent on the temporal change in the terminal potential, and the substrate terminal configured to receive a second drive signal dependent on the load voltage. 8. The circuit arrangement as claimed in claim 1, wherein the maximum value of the first current is less than a current supplied by the first current source arrangement. 9. The circuit arrangement as claimed in claim 1, further comprising a second drive unit configured to provide on-state driving of the power transistor, the second drive unit having a second drive unit output coupled to the control terminal of the power transistor, the second drive unit including a third current source arrangement connected between the second drive unit output and the first drive potential. 10. A circuit arrangement comprising: a power transistor having a control terminal and first and second load path terminals, the first load path terminal being connected to a terminal for supply potential via an inductance-exhibiting line and the second load path terminal configured to be connected to a load, at least a first current source connected between the output and a first drive potential, the first current source switchably coupled to the control terminal and configured to provide a discharge current; at least a second current source switchably coupled to the control terminal and configured to provide a first current that is dependent on an upward integration of a temporal change in a terminal potential at the first load path terminal starting from a time in which a rise in the terminal potential is produced on the inductance-exibiting line. 11. The circuit arrangement as claimed in claim 10, further comprising a control unit configured to switchably couple the second current source to the control terminal during at least a portion of an off-cycle of the first drive potential. 12. The circuit arrangement as claimed in claim 11, wherein the control unit includes: a differentiator operably coupled to the terminal potential of the first load path terminal; and an integrator coupled to the differentiator. 13. The circuit arrangement as claimed in claim 12, wherein the integrator further includes: an integration circuit coupled to generate a control output signal, the control output signal configured to control a level of the first current generated by the second current source; a first switch coupled between the integration circuit and the second current source, the first switch configured to couple the integration circuit and the second current source after the terminal potential at the first load path terminal reaches approximately a maximum value. 14. The circuit arrangement as claimed in claim 13, wherein the integrator further includes a second switch disposed between the integration circuit and the differentiator, the second switch configured to disconnect the integration circuit and the differentiator after the terminal potential at the first load path terminal reaches approximately the maximum value. 15. The circuit arrangement as claimed in claim 12, further comprising a third current source operable to provide an additional component of the first current, the additional component dependent on a load voltage. 16. The circuit arrangement as claimed in claim 15, the second current source arrangement is further configured to provide the additional component such that the additional component is related to said load voltage via a nonlinear characteristic curve. 17. The circuit arrangement as claimed in claim 10, further comprising a third current source operable to provide an additional component of the first current, the additional component dependent on a load voltage. 18. The circuit arrangement as claimed in claim 17, the second current source arrangement is further configured to provide the additional component such that the additional component is related to said load voltage via a nonlinear characteristic curve. 19. The circuit arrangement as claimed in claim 10, wherein the power transistor comprises a MOSFET.

이 특허에 인용된 특허 (13)

이 특허를 인용한 특허 피인용횟수: 10

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특허 상세정보

Circuit arrangement having a power transistor and a drive circuit for the power transistor

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이 특허에 인용된 특허 (13)

이 특허를 인용한 특허 피인용횟수: 10

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Circuit arrangement having a power transistor and a drive circuit for the power transistor

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이 특허에 인용된 특허 (13)

이 특허를 인용한 특허 피인용횟수: 10

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