Providing predictable scheduling of programs using repeating precomputed schedules on discretely scheduled and/or multiprocessor operating systems
원문보기
IPC분류정보
국가/구분
United States(US) Patent
등록
국제특허분류(IPC7판)
G06F-009/00
G06F-015/173
G06F-015/16
출원번호
US-0262643
(2005-10-31)
등록번호
US-7409689
(2008-08-05)
발명자
/ 주소
Jones,Michael B.
Regehr,John
출원인 / 주소
Microsoft Corporation
대리인 / 주소
Lee & Hayes, PLLC
인용정보
피인용 횟수 :
6인용 특허 :
27
초록▼
The present invention provides providing predictable scheduling of programs using repeating precomputed schedules on discretely scheduled and/or multiprocessor operating systems. In one embodiment, a scheduler accesses an activity scheduling graph. The activity scheduling graph is comprised of nodes
The present invention provides providing predictable scheduling of programs using repeating precomputed schedules on discretely scheduled and/or multiprocessor operating systems. In one embodiment, a scheduler accesses an activity scheduling graph. The activity scheduling graph is comprised of nodes each representing a recurring execution interval, and has one root, one or more leaves, and at least one path from the root to each leaf. Each node is on at least one path from the root to a leaf, and the number of times the execution interval represented by each node occurs during the traversal of the graph is equal to the number of paths from the root to a leaf that the node is on. Each node has associated with it an execution interval length, and is adapted to being dedicated to executing the threads of a single activity. There may be one scheduling graph for each processor, or a scheduling graph may traverse multiple processors. Start and end times for reservations and constraints are adjusted to compensate for the granularity of the clock of the system. Furthermore, the scheduler may use an existing priority-based scheduler in order to cause scheduling decisions it has made to be acted upon.
대표청구항▼
We claim: 1. A computer implementable method for a continuous-clock computer system having a plurality of processors comprising: receiving an activity comprising at least one of: a constraint for a thread in the activity specifying a desired earliest start time, amount of requested execution time,
We claim: 1. A computer implementable method for a continuous-clock computer system having a plurality of processors comprising: receiving an activity comprising at least one of: a constraint for a thread in the activity specifying a desired earliest start time, amount of requested execution time, and a deadline; and, a reservation for the activity specifying a recurring desired number of time units within a desired period; determining one of the plurality of processors for which execution of the activity and threads within the activity that are to be scheduled, based on a heuristic; and, scheduling the activity and the constraints for execution on the determined one of the plurality of processors, including inserting the activity and the constraints on a schedule for the determined one of the plurality of processors. 2. A method of claim 1, wherein the heuristic comprises determining the least loaded of the plurality of processors. 3. A method of claim 1, wherein the heuristic comprises determining a processor having other activities scheduled for execution thereon that are related to the activity. 4. A method of claim 1, wherein the heuristic comprises determining a processor having other activities scheduled for execution thereon that have a similar period to the desired period. 5. A method of claim 1, wherein the heuristic comprises randomly selecting a processor. 6. A method of claim 1, wherein the heuristic comprises performing an exhaustive search. 7. A method of claim 1, wherein the schedule is specific to the determined one of the plurality of processors. 8. A method of claim 1, wherein the schedule is specific to a sub-plurality of the processors including the determined one of the plurality of processors. 9. A method of claim 1, wherein the schedule is for all the plurality of processors including the determined one of the plurality of processors. 10. A method of claim 1, wherein the computer system has an existing scheduler, and wherein the scheduling is performed utilizing the existing scheduler. 11. A method of claim 10, wherein the existing scheduler uses unreserved time slots to schedule otherwise unscheduled threads. 12. A method of claim 11, wherein the existing scheduler also schedules scheduled threads during unreserved time slots. 13. A computer-readable medium having computer-useable instructions embodied thereon for executing the method of claim 1. 14. A computer-implementable method for a continuous-clock computer system having, a plurality of processors comprising: receiving an activity comprising at least one of: a constraint for a thread in the activity specifying a desired earliest start time, an amount of requested execution time, and a deadline; and, a reservation for the activity specifying a recurring desired number of time units within a desired period; determining at least one of the plurality of processors for which execution of the activity and threads within the activity that are to be scheduled, based on a heuristic; and, scheduling the activity and the constraints for execution on the determined one of the plurality of processors, including inserting the activity and the constraints on a schedule for the determined at least one of the plurality of processors. 15. A method of claim 14, wherein determining at least one of the plurality of processors comprises determining a single one of the plurality of processors. 16. A method of claim 14, wherein determining at least one of the plurality of processors comprises determining whether the activity fits on a single one of the plurality of processors, and upon determining that the activity does not fit on a single one of the plurality of processors, splitting the activity onto at least two of the plurality of processors. 17. A computer-readable medium having computer-useable instructions embodied thereon for executing the method of claim 14. 18. A system for scheduling a plurality of activities for each of a plurality of processors in a continuous-clock computer system, comprising: a scheduling facility configured to: receive an activity to be performed by at least one of the processors; receive at least one constraint for processing the activity; identify at least one of the plurality of processors to process the activity based on a heuristic; and, generate a schedule for at least one the identified processor, the schedule including the activity and the at least one constraint; and a scheduling status data structure operably coupled with the scheduling facility and the processors, and being configured to: receive the schedule from the scheduling facility; store the schedule; and provide access to the processors such that the identified processor is able to identify the activity and the at least one constraint. 19. A system of claim 18, wherein the at least one constraint includes an activity constraint or a thread constraint for a thread included in the activity, the at least one constraint specifying at least one of: a desired earliest start time; an amount of requested execution time; a deadline; and, a reservation for the activity specifying a recurring desired number of time units within a desired period. 20. A system of claim 18, wherein the schedule includes one of: a single scheduling graph scheduling the activities for each of the plurality of processors; and a plurality of individual scheduling graphs, each of the plurality of individual scheduling graphs scheduling the activities for one of the processors.
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이 특허에 인용된 특허 (27)
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