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Lanthanum aluminum oxynitride dielectric films 원문보기

IPC분류정보
국가/구분 United States(US) Patent 등록
국제특허분류(IPC7판)
  • H01L-021/31
  • H01L-021/02
출원번호 US-0216474 (2005-08-31)
등록번호 US-7410910 (2008-08-12)
발명자 / 주소
  • Ahn,Kie Y.
  • Forbes,Leonard
출원인 / 주소
  • Micron Technology, Inc.
대리인 / 주소
    Schwegman, Lundberg & Woessner, P.A.
인용정보 피인용 횟수 : 54  인용 특허 : 272

초록

Electronic apparatus and methods of forming the electronic apparatus include a lanthanum aluminum oxynitride film on a substrate for use in a variety of electronic systems. The lanthanum aluminum oxynitride film may be structured as one or more monolayers. The lanthanum aluminum oxynitride film may

대표청구항

What is claimed is: 1. A method comprising: forming a lanthanum aluminum oxynitride film in an integrated circuit on a substrate including forming the lanthanum aluminum oxynitride film by atomic layer deposition, the atomic layer deposition having one or more cycles, each cycle including: performi

이 특허에 인용된 특허 (272)

  1. Noble, Wendell P.; Forbes, Leonard; Ahn, Kie Y., 4 F2 folded bit line DRAM cell structure having buried bit and word lines.
  2. Wendell P. Noble ; Leonard Forbes ; Kie Y. Ahn, 4 F2 folded bit line dram cell structure having buried bit and word lines.
  3. Forbes Leonard ; Geusic Joseph E., Alternate method and structure for improved floating gate tunneling devices.
  4. Forbes Leonard ; Geusic Joseph E., Alternate method and structure for improved floating gate tunneling devices using textured surface.
  5. Gadgil, Prasad Narhar, Apparatus for atomic layer chemical vapor deposition.
  6. Ahn,Kie Y.; Forbes,Leonard, Atomic layer deposited HfSiON dielectric films wherein each precursor is independendently pulsed.
  7. Ahn,Kie Y.; Forbes,Leonard, Atomic layer deposited Zr-Sn-Ti-O films.
  8. Ahn, Kie Y.; Forbes, Leonard, Atomic layer deposited Zr-Sn-Ti-O films using TiI4.
  9. Ahn,Kie Y.; Forbes,Leonard, Atomic layer deposited ZrAlOdielectric layers including ZrAlO.
  10. Ahn,Kie Y.; Forbes,Leonard, Atomic layer deposited ZrTiOfilms.
  11. Ahn,Kie Y.; Forbes,Leonard, Atomic layer deposited dielectric layers.
  12. Ahn,Kie Y.; Forbes,Leonard, Atomic layer deposited lanthanide doped TiOx dielectric films.
  13. Ahn,Kie Y.; Forbes,Leonard, Atomic layer deposited nanolaminates of HfO/ZrOfilms as gate dielectrics.
  14. Ahn, Kie Y.; Forbes, Leonard, Atomic layer deposited nanolaminates of HfO2/ZrO2 films as gate dielectrics.
  15. Akram, Salman; Ahn, Kie Y.; Forbes, Leonard, Atomic layer deposition (ALD) high permeability layered magnetic films to reduce noise in high speed interconnection.
  16. Paranjpe,Ajit P.; Gopinath,Sanjay; Omstead,Thomas R.; Bubber,Randhir S.; Mao,Ming, Atomic layer deposition for fabricating thin films.
  17. Ahn,Kie Y.; Forbes,Leonard, Atomic layer-deposited LaAlO3 films for gate dielectrics.
  18. Ahn,Kie Y.; Forbes,Leonard, Atomic layer-deposited hafnium aluminum oxide.
  19. Ibok, Effiong; Zheng, Wei; Tripsas, Nicholas H.; Ramsbey, Mark T.; Cheung, Fred T K, Bi-layer floating gate for improved work function between floating gate and a high-K dielectric layer.
  20. Ahn, Kie Y.; Forbes, Leonard, Capacitor structure forming methods.
  21. Kashiwaya Makoto,JPX ; Nakada Junji,JPX, Carbon layer forming method.
  22. Kashiwaya, Makoto; Nakada, Junji, Carbon layer forming method.
  23. Noble, Wendell P.; Forbes, Leonard, Circuit and method for a folded bit line memory cell with vertical transistor and trench capacitor.
  24. Leonard Forbes, Circuits and methods for a memory cell with a trench plate trench capacitor and a vertical bipolar read device.
  25. Leonard Forbes, Circuits and methods for a memory cell with a trench plate trench capacitor and a vertical bipolar read device.
  26. Leonard Forbes, Circuits and methods for a memory cell with a trench plate trench capacitor and a vertical bipolar read device.
  27. Leonard Forbes, Circuits and methods for a memory cell with a trench plate trench capacitor and a vertical bipolar read device.
  28. Forbes Leonard ; Geusic Joseph E. ; Ahn Kie Y., Circuits with a trench capacitor having micro-roughened semiconductor surfaces and methods for forming the same.
  29. Masujima Sho,JPX ; Miyauchi Eisaku,JPX ; Miyajima Toshihiko,JPX ; Watanabe Hideaki,JPX, Clean transfer method and apparatus therefor.
  30. Ahn, Kie Y.; Forbes, Leonard, Composite dielectric forming methods and composite dielectrics.
  31. Czubatyj Wolodymyr ; Ovshinsky Stanford R. ; Strand David A. ; Klersy Patrick ; Kostylev Sergey ; Pashmakov Boil, Composite memory material comprising a mixture of phase-change memory material and dielectric material.
  32. Chen, Tung-Yu; Lai, Han-Chung, Contact structure and manufacturing method thereof.
  33. Farrar,Paul A.; Eldridge,Jerome M., Controlling diffusion in doped semiconductor regions.
  34. Ahn, Kie Y.; Forbes, Leonard, Copper technology for ULSI metallization.
  35. Forbes, Leonard, DRAM cells with repressed floating gate memory, low tunnel barrier interpoly insulators.
  36. Forbes, Leonard, DRAM cells with repressed floating gate memory, low tunnel barrier interpoly insulators.
  37. Forbes,Leonard, DRAM cells with repressed floating gate memory, low tunnel barrier interpoly insulators.
  38. Cabral, Jr.,Cyril; Callegari,Alessandro C.; Gribelyuk,Michael A.; Jamison,Paul C.; Lacey,Dianne L.; McFeely,Fenton R.; Narayanan,Vijay; Neumayer,Deborah A.; Ranade,Pushkar; Zafar,Sufi, Deposition of hafnium oxide and/or zirconium oxide and fabrication of passivated electronic structures.
  39. Sager,Brian M., Device based on coated nanoporous structure.
  40. Ahn,Kie Y.; Forbes,Leonard, Devices with HfSiON dielectric films which are Hf-O rich.
  41. Ahn,Kie Y.; Forbes,Leonard, Dielectric layer forming method and devices formed therewith.
  42. Marsh,Eugene P., Dielectric material forming methods.
  43. Baker, Frank Kelsey, Dielectric storage memory cell having high permittivity top dielectric and method therefor.
  44. Baker,Frank Kelsey, Dielectric storage memory cell having high permittivity top dielectric and method therefor.
  45. Yang,Jean Y.; Erhardt,Jeff P.; Tabery,Cyrus; Qian,Weidong; Ramsbey,Mark T.; Park,Jaeyong; Kamal,Tazrien, Disposable hard mask for memory bitline scaling.
  46. Ahn, Kie; Forbes, Leonard, Doped aluminum oxide dielectrics.
  47. Ahn, Kie; Forbes, Leonard, Doped aluminum oxide dielectrics.
  48. Fally Jacques,FRX, Dynamic distance and position sensor and method of measuring the distance and the position of a surface using a sensor.
  49. Kawasaki, Ritsuko; Kasahara, Kenji; Ohtani, Hisashi, EL display device with a TFT.
  50. Lee Woo-Hyeong ; Manchanda Lalita, Electronic components with doped metal oxide dielectric materials and a process for making electronic components with do.
  51. Colombo,Luigi, Encapsulated MOS transistor gate structures and methods for making the same.
  52. Colombo,Luigi, Encapsulated MOS transistor gate structures and methods for making the same.
  53. Meng, Shuang; Derderian, Garo J.; Sandhu, Gurtej Singh, Enhanced atomic layer deposition.
  54. Ahn, Kiey Y.; Forbes, Leonard, Evaporated LaA1O3 films for gate dielectrics.
  55. Ahn, Kie Y.; Forbes, Leonard, Evaporation of Y-Si-O films for medium-K dielectrics.
  56. Ahn, Kie Y.; Forbes, Leonard, Evaporation of Y-Si-O films for medium-k dielectrics.
  57. Ahn, Kie Y.; Forbes, Leonard, Field emission display having porous silicon dioxide layer.
  58. Ahn, Kie Y.; Forbes, Leonard, Field emission display having reduced power requirements and method.
  59. Noble, Wendell P.; Forbes, Leonard, Field programmable logic arrays with vertical transistors.
  60. Wendell P. Noble ; Leonard Forbes, Field programmable logic arrays with vertical transistors.
  61. Ahn, Kie Y.; Forbes, Leonard, Formation of metal oxide gate dielectric.
  62. Kie Y. Ahn ; Leonard Forbes, Formation of metal oxide gate dielectric.
  63. Ahn, Kie Y.; Forbes, Leonard, Gate oxides, and methods of forming.
  64. Forbes, Leonard; Eldridge, Jerome M., Graded composition gate insulators to reduce tunneling barriers in flash memory devices.
  65. Forbes, Leonard; Eldridge, Jerome M., Graded composition gate insulators to reduce tunneling barriers in flash memory devices.
  66. Eldridge,Jerome M.; Ahn,Kie Y.; Forbes,Leonard, Graded composition metal oxide tunnel barrier interpoly insulators.
  67. Eldridge,Jerome M.; Ahn,Kie Y.; Forbes,Leonard, Graded composition metal oxide tunnel barrier interpoly insulators.
  68. Nguyen, Bich-Yen; Zhou, Hong-Wei; Wang, Xiao-Ping, High K dielectric film.
  69. Akram,Salman; Ahn,Kie Y.; Forbes,Leonard, High permeability layered magnetic films to reduce noise in high speed interconnection.
  70. Colombo, Luigi; Chambers, James J.; Rotondaro, Antonio L. P.; Visokay, Mark R., High temperature interface layer growth for high-k gate dielectric.
  71. Colombo, Luigi; Quevedo-Lopez, Manuel; Chambers, James J.; Visokay, Mark R.; Rotondaro, Antonio L. P., High-k gate dielectric with uniform nitrogen profile and methods for making the same.
  72. Ahn, Kie Y.; Forbes, Leonard, High-quality praseodymium gate dielectrics.
  73. Ahn, Kie Y.; Forbes, Leonard, Highly reliable amorphous high-k gate dielectric ZrOXNY.
  74. Ahn, Kie Y.; Forbes, Leonard, Highly reliable gate oxide and method of fabrication.
  75. Forbes,Leonard, In service programmable logic arrays with low tunnel barrier interpoly insulators.
  76. Forbes Leonard ; Geusic Joseph E., Information handling system having improved floating gate tunneling devices.
  77. Farrar,Paul A., Integrated circuit cooling system and method.
  78. Forbes, Leonard; Eldridge, Jerome M.; Ahn, Kie Y., Integrated circuit memory device and method.
  79. Geusic Joseph E. ; Ahn Kie Y. ; Forbes Leonard, Integrated circuits using high aspect ratio vias through a semiconductor wafer and method for forming same.
  80. Geusic Joseph E. ; Ahn Kie Y. ; Forbes Leonard, Integrated circuits using optical fiber interconnects formed through a semiconductor wafer and methods for forming same.
  81. Geusic, Joseph E.; Ahn, Kie Y.; Forbes, Leonard, Integrated circuits using optical fiber interconnects formed through a semiconductor wafer and methods for forming same.
  82. Geusic Joseph E. ; Ahn Kie Y. ; Forbes Leonard, Integrated circuits using optical waveguide interconnects formed through a semiconductor wafer and methods for forming same.
  83. Geusic, Joseph E.; Ahn, Kie Y.; Forbes, Leonard, Integrated circuits using optical waveguide interconnects formed through a semiconductor wafer and methods for forming same.
  84. Ahn, Kie Y.; Forbes, Leonard, Integrated decoupling capacitors.
  85. Wagner, Sigurd; Chen, Yu, Inverter made of complementary p and n channel transistors using a single directly-deposited microcrystalline silicon film.
  86. Ahn,Kie Y.; Forbes,Leonard, Lanthanide doped TiOdielectric films.
  87. Ahn,Kie Y.; Forbes,Leonard, Lanthanide doped TiOdielectric films by plasma oxidation.
  88. Ahn, Kie Y.; Forbes, Leonard, Lanthanide doped TiOx dielectric films.
  89. Ahn, Kie Y.; Forbes, Leonard, Lanthanide doped TiOx dielectric films by plasma oxidation.
  90. Ahn,Kie Y.; Forbes,Leonard, Lanthanide oxide / hafnium oxide dielectric layers.
  91. Ahn,Kie Y.; Forbes,Leonard, Lanthanide oxide / hafnium oxide dielectric layers.
  92. Ahn,Kie Y.; Forbes,Leonard, Lanthanide oxide / hafnium oxide dielectrics.
  93. Ahn,Kie Y.; Forbes,Leonard, Lanthanide oxide dielectric layer.
  94. Ahn,Kie Y.; Forbes,Leonard, Lanthanide oxide/hafnium oxide dielectrics.
  95. Ahn,Kie; Forbes,Leonard, Lanthanide oxide/zirconium oxide atomic layer deposited nanolaminate gate dielectrics.
  96. Ahn,Kie Y.; Forbes,Leonard, Lanthanum hafnium oxide dielectrics.
  97. Maria, Jon-Paul; Kingon, Angus Ian, Lanthanum oxide-based dielectrics for integrated circuit capacitors.
  98. Ahn, Kie Y.; Forbes, Leonard, Low-temperature grown high quality ultra-thin CoTiO3 gate dielectrics.
  99. Ahn, Kie Y.; Forbes, Leonard, Low-temperature grown high-quality ultra-thin praseodymium gate dielectrics.
  100. Ahn,Kie Y.; Forbes,Leonard, Low-temperature growth high-quality ultra-thin praseodymium gate dieletrics.
  101. Visokay,Mark; Colombo,Luigi, MOS transistor gates with doped silicide and methods for making the same.
  102. Yu, Bin; Xiang, Qi, MOSFET device having high-K dielectric layer.
  103. Utsunomiya Hajime (Nagano JPX) Uchiyama Kenji (Nagano JPX) Kosuda Masanori (Nagano JPX) Inoue Hiroyasu (Nagano JPX), Magneto-optical disc with intermediate film layer between a recording film and a dielectric film.
  104. Uchiyama Kenji (Nagano JPX) Fujioka Hirokazu (Nagano JPX) Shibahara Masanori (Nagano JPX), Magneto-optical disk.
  105. Uchiyama Kenji (Nagano JPX) Shibahara Masanori (Nagano JPX) Naganawa Michiki (Nagano JPX), Magneto-optical disk.
  106. Utsunomiya Hajime (Nagano JPX) Shibahara Masanori (Nagano JPX), Magneto-optical disk having lands and grooves for recording information.
  107. Utsunomiya Hajime (Nagano JPX), Magneto-optical recording medium.
  108. Utsunomiya Hajime (Nagano JPX) Uchiyama Kenji (Nagano JPX) Kosuda Masanori (Nagano JPX) Inoue Hiroyasu (Nagano JPX), Magneto-optical recording medium.
  109. Utsunomiya Hajime (Nagano JPX) Kosuda Masanori (Nagano JPX), Magnetooptical recording medium.
  110. Forbes Leonard ; Noble Wendell P., Memory address decode array with vertical transistors.
  111. Leonard Forbes ; Wendell P. Noble, Memory address decode array with vertical transistors.
  112. Noble, Wendell P.; Forbes, Leonard; Ahn, Kie Y., Memory cell having a vertical transistor with buried source/drain and dual gates.
  113. Wendell P. Noble ; Leonard Forbes ; Kie Y. Ahn, Memory cell having a vertical transistor with buried source/drain and dual gates.
  114. Forbes Leonard ; Noble Wendell P. ; Ahn Kie Y., Memory cell with vertical transistor and buried word and body lines.
  115. Leonard Forbes ; Wendell P. Noble ; Kie Y. Ahn, Memory cell with vertical transistor and buried word and body lines.
  116. Ovshinsky Standford R. ; Czubatyj Wolodymyr ; Strand David A. ; Klersy Patrick J. ; Kostylev Sergey ; Pashmakov Boil, Memory element with memory material comprising phase-change material and dielectric material.
  117. Forbes,Leonard; Ahn,Kie Y., Memory utilizing oxide nanolaminates.
  118. Forbes,Leonard; Ahn,Kie Y., Memory utilizing oxide-conductor nanolaminates.
  119. Visokay, Mark; Colombo, Luigi; Chambers, James J., Metal gate MOS transistors and methods for making the same.
  120. Ahn, Kie Y.; Forbes, Leonard, Method and apparatus for the fabrication of ferroelectric films.
  121. Kie Y. Ahn ; Leonard Forbes, Method and apparatus for the fabrication of ferroelectric films.
  122. Wang,Ming Fang; Chen,Chia Lin; Yang,Chih Wei; Chen,Chi Chun; Hou,Tuo Hung; Lin,Yeou Ming; Yao,Liang Gi; Chen,Shih Chang, Method and structure for forming high-k gates.
  123. Geusic, Joseph E.; Forbes, Leonard; Ahn, Kie Y., Method and structure for high capacitance memory cells.
  124. Geusic, Joseph E.; Forbes, Leonard; Ahn, Kie Y., Method and structure for high capacitance memory cells.
  125. Sharan Sujit ; Sandhu Gurtej S., Method for PECVD deposition of selected material films.
  126. Basceri, Cem; Gealy, Dan; Sandhu, Gurtej S., Method for controlling deposition of dielectric films.
  127. Farrar,Paul A.; Eldridge,Jerome M., Method for controlling diffusion in semiconductor regions.
  128. Chang, Jane; Lin, You-Sheng; Kepten, Avishai; Sendler, Michael; Levy, Sagy; Bloom, Robin, Method for depositing a coating having a relatively high dielectric constant onto a substrate.
  129. Yamazaki, Shunpei; Arai, Yasuyuki, Method for fabricating a semiconductor device.
  130. Rotondaro, Antonio L. P.; Visokay, Mark Robert; Chambers, James J.; Colombo, Luigi, Method for fabricating split gate transistor device having high-k dielectrics.
  131. Visokay,Mark R.; Colombo,Luigi; Chambers,James J.; Rotondaro,Antonio L. P.; Bu,Haowen, Method for fabricating transistor gate structures and gate dielectrics thereof.
  132. Geusic Joseph E. ; Forbes Leonard ; Ahn Kie Y., Method for forming high capacitance memory cells.
  133. Geusic, Joseph E.; Ahn, Kie Y.; Forbes, Leonard, Method for forming integrated circuits using high aspect ratio vias through a semiconductor wafer.
  134. Kim Ki Bum,KRX ; Yoon Tae Sik,KRX ; Kwon Jang Yeon,KRX, Method for forming quantum dot in semiconductor device and a semiconductor device resulting therefrom.
  135. Ahn, Kie Y.; Forbes, Leonard, Method for forming single electron resistor memory.
  136. Rotondaro,Antonio L. P.; Mercer,Douglas E.; Colombo,Luigi; Visokay,Mark Robert; Bu,Haowen; Bevan,Malcolm John, Method for integrating high-k dielectrics in transistor devices.
  137. Ahn, Kie Y.; Forbes, Leonard, Method for making a ferroelectric memory transistor.
  138. Utsunomiya Hajime,JPX ; Kosuda Masanori,JPX ; Shingai Hiroshi,JPX, Method for making an optical recording medium.
  139. Kawasaki, Ritsuko; Kasahara, Kenji; Yamazaki, Shunpei, Method for manufacturing a semiconductor device.
  140. Ritsuko Kawasaki JP; Kenji Kasahara JP; Shunpei Yamazaki JP, Method for manufacturing a semiconductor device.
  141. Kawasaki, Ritsuko; Kasahara, Kenji; Yamazaki, Shunpei, Method for manufacturing a semiconductor device using laser light.
  142. Takahashi Makoto,JPX ; Utsunomiya Hajime,JPX, Method for preparing optical recording medium.
  143. Tominaga Junji (Nagano JPX) Inaba Ryo (Nagano JPX) Haratani Susumu (Chiba JPX), Method for preparing phase change optical recording medium.
  144. Ahn,Kie Y.; Forbes,Leonard, Method including forming gate dielectrics having multiple lanthanide oxide layers.
  145. Ahn, Kie Y.; Forbes, Leonard, Method of fabricating a highly reliable gate oxide.
  146. Kenji Kasahara JP, Method of fabricating a semiconductor device.
  147. Leonard Forbes ; Kie Y. Ahn, Method of fabricating a semiconductor-on-insulator memory cell with buried word and body lines.
  148. Kashiwaya, Makoto; Nakada, Junji, Method of fabricating thermal head.
  149. Lee, Jang-Eun; Park, Sun-Hoo; Son, Jung-Hoon, Method of forming a quantum dot and a gate electrode using the same.
  150. Lai,Joey; Lur,Water, Method of forming a semi-insulating region.
  151. Forbes, Leonard; Ahn, Kie Y., Method of forming a weak ferroelectric transistor.
  152. Geusic, Joseph E.; Ahn, Kie Y.; Forbes, Leonard, Method of forming an optical fiber interconnect through a semiconductor wafer.
  153. Alain E. Kaloyeros ; Ana Londergan ; Barry Arkles, Method of interlayer mediated epitaxy of cobalt silicide from low temperature chemical vapor deposition of cobalt.
  154. Ahn, Kie Y.; Forbes, Leonard, Method of making a chip packaging device having an interposer.
  155. Ritsuko Kawasaki JP; Kenji Kasahara JP; Hisashi Ohtani JP, Method of manufacturing a semiconductor device with TFT.
  156. Ahn, Kie Y.; Forbes, Leonard, Method of manufacturing a single electron resistor memory device.
  157. Ahn, Kie Y.; Forbes, Leonard, Methods and apparatus for making integrated-circuit wiring from copper, silver, gold, and other metals.
  158. Ahn,Kie Y.; Forbes,Leonard, Methods for atomic-layer deposition of aluminum oxides in integrated circuits.
  159. Ahn, Kie Y.; Forbes, Leonard, Methods for forming dielectric materials and methods for forming semiconductor devices.
  160. Alessandro Cesare Callegari ; Fuad Elias Doany ; Evgeni Petrovich Gousev ; Theodore Harold Zabel, Methods for forming metal oxide layers with enhanced purity.
  161. Visokay, Mark; Chambers, James Joseph; Colombo, Luigi; Rotondaro, Antonio Luis Pacheco, Methods for sputter deposition of high-k dielectric films.
  162. Ahn, Kie Y., Methods, systems, and apparatus for uniform chemical-vapor depositions.
  163. Adetutu,Olubunmi O.; Luo,Tien Ying; Tseng,Hsing H., Multi-layer dielectric containing diffusion barrier material.
  164. Yanjun Ma ; Yoshi Ono, Multilayer dielectric stack and method.
  165. Ahn, Kie Y.; Forbes, Leonard; Eldridge, Jerome M., Multilevel copper interconnect with double passivation.
  166. Forbes, Leonard, Multilevel semiconductor-on-insulator structures and circuits.
  167. Chen Wei ; Smith ; III Theoren Perlee ; Tiwari Sandip, Nano-structure memory device.
  168. Forbes, Leonard, Nanocrystal write once read only memory for archival storage.
  169. Chindalore, Gowrishankar L.; Ingersoll, Paul A.; Swift, Craig T.; Hoefler, Alexander B., Non-volatile memory device and method for forming.
  170. Arami Junichi,JPX ; Ishikawa Kenji,JPX ; Kitamura Masayuki,JPX, One-by-one type heat-processing apparatus.
  171. Tominaga Junji (Nagano JPX) Haratani Susumu (Chiba JPX) Inaba Ryo (Nagano JPX) Kuwahara Tsuneo (Nagano JPX), Optical information medium.
  172. Inoue,Hiroyasu; Mishima,Koji; Aoshima,Masaki; Hirata,Hideki; Utsunomiya,Hajime, Optical information recording medium.
  173. Inoue,Hiroyasu; Mishima,Koji; Aoshima,Masaki; Hirata,Hideki; Utsunomiya,Hajime, Optical information recording medium.
  174. Inoue,Hiroyasu; Mishima,Koji; Aoshima,Masaki; Hirata,Hideki; Utsunomiya,Hajime, Optical information recording medium.
  175. Inoue,Hiroyasu; Mishima,Koji; Aoshima,Masaki; Hirata,Hideki; Utsunomiya,Hajime, Optical information recording medium.
  176. Inoue,Hiroyasu; Mishima,Koji; Aoshima,Masaki; Hirata,Hideki; Utsunomiya,Hajime, Optical information recording medium.
  177. Inoue,Hiroyasu; Mishima,Koji; Aoshima,Masaki; Hirata,Hideki; Utsunomiya,Hajime, Optical information recording medium.
  178. Inoue,Hiroyasu; Mishima,Koji; Aoshima,Masaki; Hirata,Hideki; Utsunomiya,Hajime, Optical information recording medium.
  179. Judge,John S.; Shao,Jiqun; Goller,Warren W., Optical recording article.
  180. Saito Takao,JPX ; Shingai Hiroshi,JPX ; Kato Tatsuya,JPX ; Utsunomiya Hajime,JPX ; Yanagiuchi Katsuaki,JPX, Optical recording material and its fabrication method.
  181. Tominaga Junji,JPX ; Kikukawa Takashi,JPX ; Kuribayashi Isamu,JPX ; Takahashi Makoto,JPX, Optical recording material, and optical recording medium.
  182. Handa Tokuhiko (Nagano JPX) Inaba Ryo (Nagano JPX) Haratani Susumu (Nagano JPX) Tominaga Junji (Nagano JPX), Optical recording media.
  183. Kakiuchi,Hironori; Inoue,Hiroyasu, Optical recording medium.
  184. Kato Tatsuya,JPX ; Utsunomiya Hajime,JPX ; Komaki Tsuyoshi,JPX ; Hirata Hideki,JPX, Optical recording medium.
  185. Takasaki,Hiroshi; Tsutsumi,Tsutomu; Shibahara,Masanori; Ishizaki,Hideki, Optical recording medium.
  186. Takashi Kikukawa JP; Hajime Utsunomiya JP, Optical recording medium.
  187. Tominaga Junji (Nagano JPX), Optical recording medium.
  188. Tominaga Junji (Nagano JPX), Optical recording medium.
  189. Tominaga Junji (Nagano JPX) Haratani Susumu (Nagano JPX) Handa Tokuhiko (Nagano JPX) Inaba Ryo (Nagano JPX), Optical recording medium.
  190. Utsunomiya Hajime,JPX ; Kato Tatsuya,JPX ; Inoue Hiroyasu,JPX, Optical recording medium.
  191. Kosuda Masanori,JPX ; Utsunomiya Hajime,JPX ; Shingai Hiroshi,JPX ; Tsukagoshi Takuya,JPX, Optical recording medium and fabrication method therefor.
  192. Haratani Susumu (Nagano JPX) Tominaga Junji (Nagano JPX), Optical recording medium and its production.
  193. Inoue, Hiroyasu; Takahashi, Makoto; Utsunomiya, Hajime, Optical recording medium and method for its initialization.
  194. Junji Tominaga JP; Isamu Kuribayashi JP; Makoto Takahashi JP; Takashi Kikukawa JP, Optical recording medium and method for making.
  195. Tominaga Junji (Nagano JPX) Dohi Hideki (Nagano JPX), Optical recording medium and method for making.
  196. Tominaga Junji (Nagano JPX) Haratani Susumu (Tokyo JPX) Handa Tokuhiko (Nagano JPX), Optical recording medium and method for making.
  197. Tominaga Junji,JPX ; Kuribayashi Isamu,JPX ; Takahashi Makoto,JPX ; Kikukawa Takashi,JPX, Optical recording medium and method for making.
  198. Takahashi Makoto,JPX ; Kikukawa Takashi,JPX ; Kuribayashi Isamu,JPX, Optical recording medium and method for preparing the same.
  199. Tsukagoshi Takuya,JPX ; Kosuda Masanori,JPX ; Shingai Hiroshi,JPX, Optical recording medium and method for preparing the same.
  200. Kikukawa Takashi,JPX ; Utsunomiya Hajime,JPX, Optical recording medium and use.
  201. Shingai, Hiroshi; Hirata, Hideki, Optical recording medium containing a substrate, an intermediate layer having therein an amorphous material, the intermediate layer having a reflective layer thereon.
  202. Takahashi Makoto,JPX ; Kikukawa Takashi,JPX ; Kuribayashi Isamu,JPX ; Tominaga Junji,JPX, Optical recording medium, and its fabrication method.
  203. Hosoda, Yasuo; Mitsumori, Ayumi; Sato, Megumi; Yamaguchi, Masataka; Iida, Tetsuya; Inoue, Hiroyasu; Mishima, Koji; Aoshima, Masaki, Optical recording medium, method for manufacturing the same and target used for sputtering process.
  204. Hosoda,Yasuo; Mitsumori,Ayumi; Sato,Megumi; Yamaguchi,Masataka; Iida,Tetsuya; Inoue,Hiroyasu; Mishima,Koji; Aoshima,Masaki, Optical recording medium, method for manufacturing the same and target used for sputtering process.
  205. Tominaga Junji (Nagano JPX) Handa Tokuhiko (Nagano JPX) Haratani Susumu (Nagano JPX) Inaba Ryo (Nagano JPX), Optical recording method and medium.
  206. Inoue,Hiroyasu; Mishima,Koji; Aoshima,Masaki; Hirata,Hideki; Utsunomiya,Hajime; Arai,Hitoshi; Tanaka,Yoshitomo, Optical recording/reproducing method and optical recording medium.
  207. Inoue,Hiroyasu; Mishima,Koji; Aoshima,Masaki; Hirata,Hideki; Utsunomiya,Hajime; Arai,Hitoshi; Tanaka,Yoshitomo, Optical recording/reproducing method and optical recording medium.
  208. Tominaga Junji (Nagano JPX) Inaba Ryo (Nagano JPX) Kosuda Masanori (Nagano JPX) Kato Tatsuya (Nagano JPX), Phase change optical recording medium.
  209. Tominaga Junji (Nagano JPX) Inaba Ryo (Nagano JPX) Haratani Susumu (Chiba JPX), Phase change optical recording medium and activation energy determining method.
  210. Nakai,Tsukasa; Ashida,Sumio; Yusu,Keiichiro; Tsukamoto,Takayuki; Oomachi,Noritake; Nakamura,Naomasa; Ichihara, Deceased,Katsutaro; Ichihara, Legal Representative,Urara, Phase-change optical recording medium.
  211. Lee,Chun Soo; Oh,Min Sub; Park,Hyung Sang, Plasma enhanced atomic layer deposition (PEALD) equipment and method of forming a conducting thin film using the same thereof.
  212. Cain John L. (Schertz TX) Relue Michael P. (San Antonio TX) Costabile Michael E. (San Antonio TX) Marsh William P. (San Antonio TX), Plasma processing apparatus.
  213. Baum Thomas H. ; Kirlin Peter S. ; Pombrik Sofia, Platinum source compositions for chemical vapor deposition of platinum.
  214. Ahn, Kie Y.; Forbes, Leonard, Porous silicon oxycarbide integrated circuit insulator.
  215. Kie Y. Ahn ; Leonard Forbes, Porous silicon oxycarbide integrated circuit insulator.
  216. Bruley, John; Cabral, Jr., Cyril; Lavoie, Christian; Wagner, Tina J.; Wang, Yun Yu; Wildman, Horati S.; Hon, Wong Kwong, Pre-anneal of CoSi, to prevent formation of amorphous layer between Ti-O-N and CoSi.
  217. Vaartstra Brian A., Precursor chemistries for chemical vapor deposition of ruthenium and ruthenium oxide.
  218. Simons Guido,DEX ; Strecker ; deceased Helmut,DEX ITX by Renate Strecker ; executor ; Molz Peter,DEX ; Schnorr Gerd,DEX ; Skrzipczyk Heinz Jurgen,DEX ; Wissmann Hans,DEX, Process and test kit for determining free active compounds in biological fluids.
  219. Doering, Kenneth; Galewski, Carl J., Processing chamber for atomic layer deposition processes.
  220. Forbes,Leonard; Eldridge,Jerome M.; Ahn,Kie Y., Programmable array logic or memory devices with asymmetrical tunnel barriers.
  221. Forbes,Leonard; Eldridge,Jerome M.; Ahn,Kie Y., Programmable array logic or memory with p-channel devices and asymmetrical tunnel barriers.
  222. Noble, Wendell P.; Forbes, Leonard, Programmable logic array with vertical transistors.
  223. Wendell P. Noble ; Leonard Forbes, Programmable logic array with vertical transistors.
  224. Forbes,Leonard, Programmable memory address and decode circuits with low tunnel barrier interpoly insulators.
  225. Forbes,Leonard, Programmable memory address and decode circuits with low tunnel barrier interpoly insulators.
  226. Forbes, Leonard; Noble, Wendell P., Programmable memory address decode array with vertical transistors.
  227. Forbes, Leonard, SRAM cells with repressed floating gate memory, low tunnel barrier interpoly insulators.
  228. Howell, W. Max, SSICM guidance and control concept.
  229. Bhattacharyya,Arup, Scalable Flash/NV structures and devices with extended endurance.
  230. Bhattacharyya,Arup, Scalable flash/NV structures and devices with extended endurance.
  231. Bhattacharyya,Arup, Scalable integrated logic and non-volatile memory.
  232. Colombo,Luigi; Chambers,James Joseph; Visokay,Mark Robert, Semiconductor CMOS devices and methods with NMOS high-k dielectric formed prior to core PMOS dielectric formation.
  233. Chambers,James Joseph; Visokay,Mark Robert; Colombo,Luigi, Semiconductor CMOS devices and methods with NMOS high-k dielectric present in core region that mitigate damage to dielectric materials.
  234. Chung, Jeong-hee; Park, In-sung; Yeo, Jae-hyun, Semiconductor capacitors having tantalum oxide layers.
  235. Kawasaki, Ritsuko; Kasahara, Kenji; Ohtani, Hisashi, Semiconductor device and a method of manufacturing the same.
  236. Kawasaki,Ritsuko; Kasahara,Kenji; Ohtani,Hisashi, Semiconductor device and a method of manufacturing the same.
  237. Aoyama, Tomonori, Semiconductor device and manufacturing method therefor.
  238. Kawasaki, Ritsuko; Kasahara, Kenji; Ohtani, Hisashi, Semiconductor device and method of fabricating the same.
  239. Li,Hong Jyh, Semiconductor device and method of manufacture thereof.
  240. Shunpei Yamazaki JP; Yasuyuki Arai JP, Semiconductor device having single crystal grains with hydrogen and tapered gate insulation layer.
  241. Kinoshita,Hiroyuki; Sun,Yu; Banerjee,Basab; Foster,Christopher M.; Behnke,John R.; Tabery,Cyrus, Semiconductor device with core and periphery regions.
  242. Jamal Ramdani ; Ravindranath Droopad ; Lyndee L. Hilt ; Kurt William Eisenbeiser, Semiconductor structure, semiconductor device, communicating device, integrated circuit, and process for fabricating the same.
  243. Kalal, Peter J.; Quesada, Mark A., Sensors, methods of manufacture and sensing methods.
  244. Forbes,Leonard, Service programmable logic arrays with low tunnel barrier interpoly insulators.
  245. Forbes,Leonard, Service programmable logic arrays with low tunnel barrier interpoly insulators.
  246. Ahn Kie Y. ; Forbes Leonard, Silicon multi-chip module packaging with integrated passive components and method of making.
  247. Chen Chih Ming,TWX, Source side injection flash EEPROM memory cell with dielectric pillar and operation.
  248. Hong,Cheong M.; Chindalore,Gowrishankar L., Source side injection storage device with spacer gates and method therefor.
  249. Ahn Kie Y. ; Forbes Leonard ; Cloud Eugene H., Structure and method for a high performance electronic packaging assembly.
  250. Ahn, Kie Y.; Forbes, Leonard; Cloud, Eugene H., Structure and method for a high-performance electronic packaging assembly.
  251. Ahn Kie Y. ; Forbes Leonard, Structure and method for dual gate oxide thicknesses.
  252. Ahn, Kie Y.; Forbes, Leonard, Structure and method for dual gate oxide thicknesses.
  253. Ahn, Kie Y.; Forbes, Leonard, Structure and method for dual gate oxide thicknesses.
  254. Ahn, Kie Y.; Forbes, Leonard, Structure and method for dual gate oxide thicknesses.
  255. Ahn, Kie Y.; Forbes, Leonard, Structures, methods, and systems for ferroelectric memory transistors.
  256. Ahn, Kie Y.; Forbes, Leonard, Structures, methods, and systems for ferroelectric memory transistors.
  257. Vaartstra,Brian A., Systems and methods of forming refractory metal nitride layers using disilazanes.
  258. Kashiwaya Makoto,JPX ; Nakata Junji,JPX, Thermal head.
  259. Kashiwaya Makoto,JPX ; Yoneda Junichi,JPX ; Noshita Taihei,JPX, Thermal head.
  260. Noshita Taihei,JPX, Thermal head.
  261. Yoneda Junichi,JPX, Thermal head.
  262. Yoneda Junichi,JPX ; Kashiwaya Makoto,JPX ; Noshita Taihei,JPX, Thermal head.
  263. Akira Yamaguchi JP, Thermal head adjusting method.
  264. Noshita Taihei,JPX ; Yoneda Junichi,JPX ; Kashiwaya Makoto,JPX, Thermal head and method of manufacturing the same.
  265. Kashiwaya Makoto,JPX ; Nakada Junji,JPX, Thermal head fabrication method.
  266. Kashiwaya, Makoto; Nakada, Junji, Thermal head lapping apparatus.
  267. Noshita Taihei,JPX ; Yoneda Junichi,JPX ; Kashiwaya Makoto,JPX, Thermal head method of manufacturing the same.
  268. Akira Yamaguchi JP, Thermal recording apparatus.
  269. Quevedo Lopez,Manuel A.; Chambers,James J.; Colombo,Luigi; Visokay,Mark R., Top surface roughness reduction of high-k dielectric materials using plasma based processes.
  270. Zoran Krivokapic, Ultra-thin fully depleted SOI device with T-shaped gate and method of fabrication.
  271. Forbes Leonard, Vertical bipolar read access for low voltage memory cell.
  272. Forbes, Leonard, Write once read only memory employing charge trapping in insulators.

이 특허를 인용한 특허 (54)

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  2. Ahn, Kie Y.; Forbes, Leonard, Apparatus having a lanthanum-metal oxide semiconductor device.
  3. Derderian, Garo J.; Sandhu, Gurtej Singh, Atomic layer deposition and conversion.
  4. Ahn, Kie Y.; Forbes, Leonard, Atomic layer deposition of a ruthenium layer to a lanthanide oxide dielectric layer.
  5. Oh, Pyeong Won; Kim, Woo Jin; Oh, Hoon Jung; Yoon, Hyo Gun; Yoon, Hyo Seob; Choi, Baik II, Capacitor for a semiconductor device and manufacturing method thereof.
  6. Ahn, Kie Y.; Forbes, Leonard, Conductive layers for hafnium silicon oxynitride.
  7. Ahn, Kie Y.; Forbes, Leonard, Conductive layers for hafnium silicon oxynitride films.
  8. Sandhu, Gurtej S.; Durcan, D. Mark, Devices with nanocrystals and methods of formation.
  9. Sandhu, Gurtej S.; Durcan, D. Mark, Devices with nanocrystals and methods of formation.
  10. Forbes, Leonard; Ahn, Kie Y.; Bhattacharyya, Arup, Dielectrics containing at least one of a refractory metal or a non-refractory metal.
  11. Forbes, Leonard; Ahn, Kie Y.; Bhattacharyya, Arup, Dielectrics containing at least one of a refractory metal or a non-refractory metal.
  12. Forbes, Leonard; Ahn, Kie Y.; Bhattacharyya, Arup, Dielectrics containing at least one of a refractory metal or a non-refractory metal.
  13. Ahn, Kie Y.; Forbes, Leonard, Electronic devices including barium strontium titanium oxide films.
  14. Ahn, Kie Y.; Forbes, Leonard, Electronic devices including barium strontium titanium oxide films.
  15. Forbes, Leonard; Eldridge, Jerome M., Flash memory with low tunnel barrier interpoly insulators.
  16. Ahn, Kie Y.; Forbes, Leonard, Gallium lanthanide oxide films.
  17. Ahn, Kie Y.; Forbes, Leonard, Gallium lanthanide oxide films.
  18. Ahn, Kie Y.; Forbes, Leonard, Gallium lathanide oxide films.
  19. Gealy, Dan; Bhat, Vishwanath; Srividya, Cancheepuram V.; Rocklein, M. Noel, Graded dielectric layers.
  20. Gealy, Dan; Bhat, Vishwanath; Srividya, Cancheepuram V.; Rocklein, M. Noel, Graded dielectric structures.
  21. Gealy, F. Daniel; Bhat, Vishwanath; Srividya, Cancheepuram V.; Rocklein, M. Noel, Graded dielectric structures.
  22. Ahn, Kie Y.; Forbes, Leonard, Hafnium tantalum oxide dielectrics.
  23. Ahn, Kie Y.; Forbes, Leonard, Hafnium tantalum oxide dielectrics.
  24. Forbes, Leonard; Ahn, Kie Y.; Bhattacharyya, Arup, Hafnium tantalum oxynitride dielectric.
  25. Forbes, Leonard; Ahn, Kie Y.; Bhattacharyya, Arup, Hafnium tantalum oxynitride dielectric.
  26. Forbes, Leonard; Ahn, Kie Y.; Bhattacharyya, Arup, Hafnium tantalum oxynitride high-k dielectric and metal gates.
  27. Ahn, Kie Y.; Forbes, Leonard, Hafnium titanium oxide films.
  28. Ahn, Kie Y.; Forbes, Leonard, HfAlOfilms for gate dielectrics.
  29. Farrar,Paul A., Integrated circuit cooling system and method.
  30. Ahn, Kie Y.; Forbes, Leonard, Lanthanide doped TiOx films.
  31. Ahn, Kie Y.; Forbes, Leonard, Lanthanum aluminum oxynitride dielectric films.
  32. Ahn, Kie Y.; Forbes, Leonard, Method of fabricating an apparatus having a lanthanum-metal oxide dielectric layer.
  33. Ahn, Kie Y.; Forbes, Leonard, Method of forming an apparatus having a dielectric containing cerium oxide and aluminum oxide.
  34. Ahn, Kie Y.; Forbes, Leonard, Methods for atomic-layer deposition.
  35. Ahn, Kie Y.; Forbes, Leonard, Methods of forming titanium silicon oxide.
  36. Ahn, Kie Y.; Forbes, Leonard, Methods of forming zirconium aluminum oxide.
  37. Ahn, Kie Y.; Forbes, Leonard, Nanolaminates of hafnium oxide and zirconium oxide.
  38. Ahn, Kie Y.; Forbes, Leonard, Structures containing titanium silicon oxide.
  39. Forbes, Leonard; Ahn, Kie Y.; Bhattacharyya, Arup, Tantalum aluminum oxynitride high-K dielectric.
  40. Forbes, Leonard; Ahn, Kie Y.; Bhattacharyya, Arup, Tantalum aluminum oxynitride high-κ dielectric.
  41. Forbes, Leonard; Ahn, Kie Y.; Bhattacharyya, Arup, Tantalum silicon oxynitride high-K dielectrics and metal gates.
  42. Forbes, Leonard; Ahn, Kie Y.; Bhattacharyya, Arup, Tantalum silicon oxynitride high-K dielectrics and metal gates.
  43. Forbes, Leonard; Ahn, Kie Y.; Bhattacharyya, Arup, Tantalum silicon oxynitride high-k dielectrics and metal gates.
  44. Ahn, Kie Y.; Forbes, Leonard, Titanium-doped indium oxide films.
  45. Ahn, Kie Y.; Forbes, Leonard, Titanium-doped indium oxide films.
  46. Masuoka, Yuri; Huang, Huan-Tsung, Transistor performance improving method with metal gate.
  47. Masuoka, Yuri; Huang, Huan-Tsung, Transistor performance improving method with metal gate.
  48. Ahn, Kie Y.; Forbes, Leonard, Zirconium-doped tantalum oxide films.
  49. Ahn, Kie Y.; Forbes, Leonard, Zirconium-doped tantalum oxide films.
  50. Ahn, Kie Y.; Forbes, Leonard, Zirconium-doped tantalum oxide films.
  51. Ahn, Kie Y.; Forbes, Leonard, Zirconium-doped tantalum oxide films.
  52. Ahn, Kie Y.; Forbes, Leonard, Zirconium-doped tantalum oxide films.
  53. Ahn, Kie Y.; Forbes, Leonard, Zr-Sn-Ti-O films.
  54. Ahn, Kie Y.; Forbes, Leonard, Zr-Sn-Ti-O films.
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