Dielectric layers containing a lanthanum hafnium oxide layer, where the lanthanum hafnium oxide layer is arranged as a structure of one or more monolayers, provide an insulating layer in a variety of structures for use in a wide range of electronic devices.
대표청구항▼
What is claimed is: 1. An electronic device comprising: a substrate having an integrated circuit; and a dielectric layer disposed on the substrate as part of the integrated circuit, the dielectric layer containing a lanthanum hafnium oxide layer and a lanthanide other than lanthanum, the lanthanum
What is claimed is: 1. An electronic device comprising: a substrate having an integrated circuit; and a dielectric layer disposed on the substrate as part of the integrated circuit, the dielectric layer containing a lanthanum hafnium oxide layer and a lanthanide other than lanthanum, the lanthanum hafnium oxide layer structured as one or more monolayers of lanthanum hafnium oxide. 2. The electronic device of claim 1, wherein the dielectric layer includes a dielectric stack having the lanthanum hafnium oxide layer on a silicon oxide layer. 3. The electronic device of claim 1, wherein the lanthanum hafnium oxide layer includes a substantial amount of La2Hf2O7. 4. The electronic device of claim 1, wherein the lanthanum hafnium oxide layer is essentially a layer of La2Hf2O7. 5. The electronic device of claim 1, wherein the lanthanum hafnium oxide layer is doped with the lanthanide other than lanthanum. 6. The electronic device of claim 1, wherein the dielectric layer includes a layer of an insulating metal oxide in addition to the lanthanum hafnium oxide layer. 7. The electronic device of claim 1, wherein the dielectric layer is structured as a nanolaminate. 8. The electronic device of claim 1, wherein the dielectric layer is structured as a capacitor dielectric in a capacitor. 9. The electronic device of claim 1, wherein the dielectric layer is structured as a gate insulator in a silicon complementary metal-oxide-semiconductor field effect (CMOS) transistor. 10. The electronic device of claim 1, wherein the dielectric layer is structured as a gate insulator on and contacting a channel region, the channel region being between a source region and a drain region of a transistor. 11. The electronic device of claim 1, wherein the dielectric layer is structured as a floating gate dielectric of a transistor, the floating gate dielectric disposed between and in contact with a floating gate and a control gate. 12. The electronic device of claim 1, wherein the integrated circuit includes an analog integrated circuit. 13. The electronic device of claim 1, wherein the integrated circuit includes a radio frequency integrated circuit. 14. The electronic device of claim 1, wherein the integrated circuit includes a mixed signal integrated circuit. 15. The electronic device of claim 1, wherein the electron device includes a memory. 16. A memory including: an array of memory cells on a substrate, a memory cell having a semiconductor device; and a dielectric layer disposed in the semiconductor device, the dielectric layer containing a lanthanum hafnium oxide layer and a lanthanide other than lanthanum, the lanthanum hafnium oxide layer structured as one or more monolayers of lanthanum hafnium oxide. 17. The memory of claim 16, wherein the dielectric layer is a gate insulator of a transistor in the memory cell. 18. The memory of claim 16, wherein the memory includes a flash memory device. 19. The memory of claim 18, wherein the dielectric layer is an inter-gate insulator between and contacting a floating gate and a control gate of a transistor in the flash memory device. 20. The memory of claim 18, wherein the dielectric layer is a gate insulator between and contacting a floating gate and a channel of a transistor in the flash memory device. 21. The memory of claim 16, wherein the dielectric layer is a dielectric of a capacitor in the memory cell. 22. The memory of claim 16, wherein the dielectric layer is a nanolaminate in a NROM flash memory device. 23. The memory of claim 16, wherein the dielectric layer includes a dielectric stack having the lanthanum hafnium oxide layer on a silicon oxide layer. 24. The memory of claim 16, wherein the lanthanum hafnium oxide layer includes a substantial amount of La2Hf2O7. 25. A system comprising: a controller; and an integrated circuit coupled to the controller, wherein at least one of the controller or integrated circuit includes a dielectric layer disposed on a substrate, the dielectric layer containing a lanthanum hafnium oxide layer and a lanthanide other than lanthanum, the lanthanum hafnium oxide layer structured as one or more monolayers of lanthanum hafnium oxide. 26. The system of claim 25, wherein the dielectric layer includes a dielectric stack having the lanthanum hafnium oxide layer on a silicon oxide layer. 27. The system of claim 25, wherein the lanthanum hafnium oxide layer includes a substantial amount of La2Hf2O7. 28. The system of claim 25, wherein the lanthanum hafnium oxide layer is doped with the lanthanide other than lanthanum. 29. The system of claim 25, wherein the integrated circuit includes a memory. 30. The system of claim 25, wherein the dielectric layer is an inter-gate insulator between and contacting a floating gate and a control gate of a transistor. 31. The system of claim 25, wherein the dielectric layer is a gate insulator between and contacting a gate and a channel of a transistor. 32. The system of claim 25, wherein the controller includes a processor. 33. The system of claim 25, wherein the integrated circuit includes a mixed signal integrated circuit. 34. The system of claim 25, wherein the system is an information handling system. 35. The system of claim 25, wherein the system is a wireless system.
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