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Method and apparatus for elimination of prolog and epilog instructions in a vector processor using data validity tags and sink counters

IPC분류정보
국가/구분 United States(US) Patent 등록
국제특허분류(IPC7판)
  • G06F-009/30
출원번호 US-0652135 (2003-08-29)
등록번호 US-7415601 (2008-08-19)
발명자 / 주소
  • May,Philip E.
  • Essick, IV,Raymond B.
  • Lucas,Brian G.
  • Moat,Kent D.
  • Norris,James M.
출원인 / 주소
  • Motorola, Inc.
인용정보 피인용 횟수 : 3  인용 특허 : 65

초록

A method and apparatus for the elimination of prolog and epilog instructions in a vector processor. To eliminate the prolog, a functional unit of the vector processor has at least one input for receiving an input data value tagged with a data validity tag and an output for outputting an intermediate

대표청구항

What is claimed is: 1. A method for executing, on a processor, a pipelined program loop having a loop body but no separately coded prolog instructions for priming the pipeline, the processor comprising a plurality of functional units coupled through an interconnection switch and controlled by a con

이 특허에 인용된 특허 (65)

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이 특허를 인용한 특허 (3)

  1. Perkins, Michael G.; Higham, Andrew J., Staged loop instructions.
  2. Nuzman, Dorit; Rosen, Ira; Zaks, Ayal, Vectorization of program code.
  3. Nuzman, Dorit; Rosen, Ira; Zaks, Ayal, Vectorization of program code.
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