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Integrated system for tool front-end workpiece handling 원문보기

IPC분류정보
국가/구분 United States(US) Patent 등록
국제특허분류(IPC7판)
  • B65G-049/07
출원번호 US-0194702 (2002-07-12)
등록번호 US-7419346 (2008-09-02)
발명자 / 주소
  • Danna,Mark
  • Hine,Roger G.
  • Bonom,Anthony C.
출원인 / 주소
  • Asyst Technologies, Inc.
대리인 / 주소
    Martine Penilla & Gencarella, LLP
인용정보 피인용 횟수 : 23  인용 특허 : 17

초록

An integrated system is disclosed for workpiece handling and/or inspection at the front end of a tool. The system comprises a rigid member of unitary construction such as a metal plate which mounts to the front of a tool associated with a semiconductor process. The front end components, including th

대표청구항

We claim: 1. A system for transporting a workpiece, comprising: a first process tool having a plate mounted to a front end of said first process tool, a load port assembly and a port door, said plate having a port door aperture and a workpiece transfer opening, said port door for moving between a o

이 특허에 인용된 특허 (17)

  1. Prentakis Antonios E. (Cambridge MA), Apparatus and method for loading and unloading wafers.
  2. Marchese-Ragona Silvio P. ; Bryant Robert ; Seelig Matthew E. ; Lindquist Dag ; McClimans Donald P. ; Merritt ; Jr. Edward J. ; Stephan John E. ; Teleska John A., Automated optical surface profile measurement system.
  3. Mizokawa, Takumi; Omori, Makoto; Takakado, Yuzo; Kawano, Hitoshi, Conveyance system.
  4. Southworth Peter R. (Mission Viejo CA) Baxter Gregory R. (Orange CA), Conveyor system.
  5. Scott Richard G. (Austin TX) Shackleton Craig R. (Austin TX) Ellis Raymond W. (Austin TX), Integrated building and conveying structure for manufacturing under ultraclean conditions.
  6. Mages Andreas,DEX ; Scheler Werner,DEX ; Blaschitz Herbert,DEX ; Schulz Alfred,DEX ; Schneider Heinz,DEX, Loading and unloading station for semiconductor processing installations.
  7. Cheng David, Method and apparatus for loading and unloading wafers from a wafer carrier.
  8. Aggarwal Ravinder ; Stevens Ronald R., Multi-stage single-drive FOUP door system.
  9. Paul Bacchi ; Paul S. Filipski, Pod load interface equipment adapted for implementation in a fims system.
  10. Miyashita Masahiro,JPX, Positioning apparatus for substrates to be processed.
  11. Akihiro Osaka JP; Hiroshi Sekiyama JP; Kouichi Noto JP; Masaki Sugawara JP, Semiconductor manufacturing method and semiconductor manufacturing apparatus.
  12. Saeki, Hiroaki; Taniyama, Yasushi, Semiconductor processing system.
  13. Ohkura Jun (Kumamoto JPX) Iida Naruaki (Kumamoto JPX) Kudou Hiroyuki (Kumamoto-ken JPX) Tateyama Masanori (Kumamoto JPX) Sakamoto Yasuhiro (Kumamoto-ken JPX), Substrate processing apparatus and substrate processing method.
  14. Blonigan, Wendell T.; White, John M., Substrate transfer shuttle having a magnetic drive.
  15. Hofmeister Christopher A., Substrate transport apparatus.
  16. Van Der Meulen, Peter, System for transporting substrates.
  17. Miller Kenneth C. (280 Easy St. ; #117 Mountain View CA 94043), Wafer transport device.

이 특허를 인용한 특허 (23)

  1. Pannese, Patrick D., Applications of neural networks.
  2. van der Meulen, Peter, Batch wafer alignment.
  3. Asakawa, Teruo, Carrying system, substrate treating device, and carrying method.
  4. Canale, Joseph Eugene; King, Jeffrey Stapleton; Trott, Gary Richard, Glass wafers for semiconductor fabrication processes and methods of making same.
  5. Canale, Joseph Eugene; King, Jeffrey Stapleton; Trott, Gary Richard, Glass wafers for semiconductors fabrication processes and methods of making same.
  6. Bonora, Anthony C.; Hine, Roger G.; Rogers, Theodore W., Loader and buffer for reduced lot size.
  7. Chen, Shih-Hung; Xiao, Ying; Lin, Chin-Hsiang, Loadport bridge for semiconductor fabrication tools.
  8. Hosek, Martin, Manipulator auto-teach and position correction system.
  9. Hosek, Martin, Manipulator auto-teach and position correction system.
  10. Pannese, Patrick D.; Kavathekar, Vinaya; van der Meulen, Peter, Methods and systems for controlling a semiconductor fabrication process.
  11. Pannese, Patrick D.; Kavathekar, Vinaya; van der Meulen, Peter, Methods and systems for controlling a semiconductor fabrication process.
  12. Pannese, Patrick D.; Kavathekar, Vinaya; van der Meulen, Peter, Methods and systems for controlling a semiconductor fabrication process.
  13. Pannese, Patrick D.; Kavathekar, Vinaya; van der Meulen, Peter, Methods and systems for controlling a semiconductor fabrication process.
  14. Pannese, Patrick D.; Kavathekar, Vinaya; van der Meulen, Peter, Methods and systems for controlling a semiconductor fabrication process.
  15. Pannese, Patrick D.; Kavathekar, Vinaya; van der Meulen, Peter, Methods and systems for controlling a semiconductor fabrication process.
  16. Hosaka, Hiroki; Akiyama, Shuji; Obikane, Tadashi, Probing apparatus and probing method.
  17. van der Meulen, Peter, Semiconductor manufacturing systems.
  18. van der Meulen, Peter; Kiley, Christopher C; Pannese, Patrick D.; Ritter, Raymond S.; Schaefer, Thomas A., Semiconductor wafer handling and transport.
  19. van der Meulen, Peter; Kiley, Christopher C; Pannese, Patrick D.; Ritter, Raymond S.; Schaefer, Thomas A., Semiconductor wafer handling and transport.
  20. van der Meulen, Peter; Kiley, Christopher C; Pannese, Patrick D.; Ritter, Raymond S.; Schaefer, Thomas A., Semiconductor wafer handling and transport.
  21. van der Meulen, Peter; Kiley, Christopher C.; Pannese, Patrick D.; Ritter, Raymond S.; Schaefer, Thomas A., Semiconductor wafer handling transport.
  22. Aguilar, Silvia R.; Wong, Scott; Witkowicki, Derek J.; Gould, Richard H.; Kristoffersen, Candi; Senn, Brandon, Stacked wafer cassette loading system.
  23. Maccari, Antonio, Tool for positioning a scanning device.
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