초록 ▼

The invention provides a semiconductor integrated circuit device provided with an SRAM that satisfies the requirements for both the SNM and the write margin with a low supply voltage. The semiconductor integrated circuit device include: multiple static memory cells provided in correspondence with mu

The invention provides a semiconductor integrated circuit device provided with an SRAM that satisfies the requirements for both the SNM and the write margin with a low supply voltage. The semiconductor integrated circuit device include: multiple static memory cells provided in correspondence with multiple word lines and multiple complimentary bit lines; multiple memory cell power supply lines that each supply an operational voltage to each of the multiple memory cells connected to the multiple complimentary bit lines each; multiple power supply circuits comprised of resistive units that each supply a power supply voltage to the memory cell power supply lines each; and a pre-charge circuit that supplies a pre-charge voltage corresponding to the power supply voltage to the complimentary bit lines, wherein the memory cell power supply lines are made to have coupling capacitances to thereby transmit a write signal on corresponding complimentary bit lines.

대표청구항 ▼

What is claimed is: 1. A semiconductor integrated circuit device provided with a SRAM memory comprising: a plurality of word lines; a plurality of complementation bit lines; a plurality of memory cells for allocated corresponding to the plurality of word lines and the plurality of complementation b

What is claimed is: 1. A semiconductor integrated circuit device provided with a SRAM memory comprising: a plurality of word lines; a plurality of complementation bit lines; a plurality of memory cells for allocated corresponding to the plurality of word lines and the plurality of complementation bit lines; a plurality of memory cell voltage lines for supplying an operational voltage to each of the plurality of memory cells; and a plurality of voltage means for supplying a power voltage to the plurality of memory cell voltage lines each, wherein each of the voltage means is a switch MOS which is turned OFF in a write state to the memory cell by a control signal basis of a memory cell write control signal and a memory cell selection signal for the corresponding complementation bit lines, wherein the power voltage is a positive voltage, wherein the switch MOS is a PMOS, and wherein the PMOS is allocated in parallel with an NMOS, and the gates of the PMOS and the NMOS are commonly connected. 2. A semiconductor integrated circuit device according to claim 1, wherein a pre-charge means is provided to the complementation bit lines, wherein the pre-charge means supplies a pre-charge voltage corresponding to the power voltage, and wherein the memory cell voltage lines have parasitic capacitances between the corresponding complementation bit lines and the memory cell voltage lines. 3. A semiconductor integrated circuit device provided with a SRAM memory comprising: a plurality of word lines; a plurality of complementation bit lines; a plurality of memory cells for allocated corresponding to the plurality of word lines and the plurality of complementation bit lines; a plurality of memory cell voltage lines for supplying an operational voltage to each of the plurality of memory cells; and a plurality of voltage means for supplying a power voltage to the plurality of memory cell voltage lines each, wherein each of the voltage means is a switch MOS which is turned OFF in a write state to the memory cell by a control signal basis of a memory cell write control signal and a memory cell selection signal for the corresponding complementation bit lines, wherein the power voltage is a positive potential, wherein the switch MOS is constructed by a PMOS, and wherein an NMOS is allocated between the memory cell voltage line and a lower limit operational voltage line to the memory cell, wherein the gate of the NMOS being connected to the gate of the PMOS. 4. A semiconductor integrated circuit device provided with a SRAM memory comprising: a plurality of word lines; a plurality of complementation bit lines; a plurality of memory cells for allocated corresponding to the plurality of word lines and the plurality of complementation bit lines; a plurality of memory cell voltage lines for supplying an operational voltage to each of the plurality of memory cells; and a plurality of voltage means for supplying a power voltage to the plurality of memory cell voltage lines each, wherein each of the voltage means is a switch MOS which is turned OFF in a write state to the memory cell by a control signal basis of a memory cell write control signal and a memory cell selection signal for the corresponding complementation bit lines, wherein the power voltage is higher than a ground voltage, wherein the switch MOS is a first PMOS, wherein a second PMOS is allocated between the memory cell voltage line and the a ground voltage, and wherein the second PMOS is switch-controlled complimentary with the first PMOS. 5. A semiconductor integrated circuit device provided with a SRAM memory comprising: a plurality of word lines; a plurality of complementation bit lines; a plurality of memory cells for allocated corresponding to the plurality of word lines and the plurality of complementation bit lines; a plurality of memory cell voltage lines for supplying an operational voltage to each of the plurality of memory cells; a plurality of voltage means for supplying a power voltage to the plurality of memory cell voltage lines each; and a word line selection means for selecting one of the plurality of word lines, wherein each of the voltage means is a switch MOS which is turned OFF in a write state to the memory cell by a control signal basis of a memory cell write control signal and a memory cell selection signal for the corresponding complementation bit lines, wherein the word line selection means includes: first and second MOS of a first conductive type connected in series between the memory cell voltage line and an output terminal; and third and fourth MOS of a second conductive type, connected in parallel between a ground voltage line and the output terminal, wherein a first control signal is provided to the gates of the first MOS and the third MOS, wherein a second control signal is provided to the gates of the second MOS and the fourth MOS, wherein the output terminal is connected to one corresponding word line of the plurality of word lines, and wherein the semiconductor integrated circuit further comprises a word driver means, wherein when the word line is selected, the first and the second MOS are turned ON and the third and the fourth MOS are turned OFF in correspondence with the first control signal and the second control signal.