최소 단어 이상 선택하여야 합니다.
최대 10 단어까지만 선택 가능합니다.
다음과 같은 기능을 한번의 로그인으로 사용 할 수 있습니다.
NTIS 바로가기다음과 같은 기능을 한번의 로그인으로 사용 할 수 있습니다.
DataON 바로가기다음과 같은 기능을 한번의 로그인으로 사용 할 수 있습니다.
Edison 바로가기다음과 같은 기능을 한번의 로그인으로 사용 할 수 있습니다.
Kafe 바로가기국가/구분 | United States(US) Patent 등록 |
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국제특허분류(IPC7판) |
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출원번호 | US-0328015 (2006-01-09) |
등록번호 | US-7420848 (2008-09-02) |
발명자 / 주소 |
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출원인 / 주소 |
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대리인 / 주소 |
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인용정보 | 피인용 횟수 : 0 인용 특허 : 502 |
A method and a system for operating bits of memory cells in a memory array, the method including applying a first operating pulse to a terminal of a first cell, the first operating pulse is intended to place the first cell into a predefined state; and applying a second operating pulse to a terminal
A method and a system for operating bits of memory cells in a memory array, the method including applying a first operating pulse to a terminal of a first cell, the first operating pulse is intended to place the first cell into a predefined state; and applying a second operating pulse to a terminal of a second cell in the set, the second operating pulse is intended to place the second cell to the predefined state, and the pulse characteristics of the second operating pulse are a function of the response of the first cell to the first operating pulse.
What is claimed is: 1. A control circuit for operating a set of memory cells in a memory array, said control circuit comprising: a charge circuit adapted to produce a first operating pulse to a terminal of a first cell intended to place the first cell into a predefined state; and a logic unit adapt
What is claimed is: 1. A control circuit for operating a set of memory cells in a memory array, said control circuit comprising: a charge circuit adapted to produce a first operating pulse to a terminal of a first cell intended to place the first cell into a predefined state; and a logic unit adapted to determine pulse characteristics of a second operating pulse as a function of the response of the first cell to the first operating pulse. 2. The control circuit according to claim 1, wherein said logic unit is further adapted to determine pulse characteristics of a third operating pulse as a function of the response of the first cell and a second cell to the first and second operating pulses, respectively. 3. The control circuit according to claim 1, wherein said logic unit is adapted to adjust the duration of said second operation pulse. 4. The control circuit according to claim 1, wherein said logic unit is adapted to adjust the amplitude of said second operation pulse. 5. The control circuit according to claim 1, further comprising a memory buffer adapted to store data received from the set of memory cells. 6. A system for operating a set of memory cells in a memory array, said system comprising: a memory array; a sense amplifier adapted to determine a response of operated cells; and a control circuit adapted to produce a first operating pulse to a terminal of a first cell intended to place the first cell into a predefined state; and adapted to determine pulse characteristics of a second operating pulse as a function of the response of the first cell to the first operating pulse. 7. The system according to claim 6, wherein said control circuit is further adapted to determine pulse characteristics of a third operating pulse as a function of the response of the first cell and a second cell to the first and second operating pulses, respectively. 8. The system according to claim 6, wherein said control circuit is adapted to adjust the duration of said second operation pulse. 9. The system according to claim 6, wherein said control circuit is adapted to adjust the amplitude of said second operation pulse.
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