IPC분류정보
국가/구분 |
United States(US) Patent
등록
|
국제특허분류(IPC7판) |
|
출원번호 |
US-0837098
(2007-08-10)
|
등록번호 |
US-7423447
(2008-09-09)
|
우선권정보 |
TW-96100242 A(2007-01-03) |
발명자
/ 주소 |
|
출원인 / 주소 |
|
대리인 / 주소 |
Thomas, Kayden, Horstemeyer & Risley
|
인용정보 |
피인용 횟수 :
2 인용 특허 :
4 |
초록
▼
A method for testing a liquid crystal display panel is provided. The gate drivers are integrated onto the panel. The method includes simultaneously inputting a clock signal, an inverted clock signal, and a pull down signal into clock signal, inverted clock signal, and pull down signal input ends of
A method for testing a liquid crystal display panel is provided. The gate drivers are integrated onto the panel. The method includes simultaneously inputting a clock signal, an inverted clock signal, and a pull down signal into clock signal, inverted clock signal, and pull down signal input ends of the gate drivers. Simultaneously input a start pulse into the start pulse input end of the gate drivers to simultaneously turn on the gate lines in the selected area and thus simultaneously turning on the pixels in the selected area. At the same time, input test signals to all the data lines. The method of testing liquid crystal display panels disclosed by the present invention may be performed separately by areas, in which the panel is divided into different sub areas and is tested one area at a time.
대표청구항
▼
What is claimed is: 1. A method for testing a liquid crystal display panel having a plurality of pixels, a plurality of gate drivers, a plurality of gate lines and a plurality of data lines, wherein each gate driver has a clock signal input, an inverted clock input, a pull down input and a start pu
What is claimed is: 1. A method for testing a liquid crystal display panel having a plurality of pixels, a plurality of gate drivers, a plurality of gate lines and a plurality of data lines, wherein each gate driver has a clock signal input, an inverted clock input, a pull down input and a start pulse input and is integrated onto the liquid crystal display panel, the method comprising: inputting a clock signal, an inverted clock signal and a pull down signal into a clock signal input, an inverted clock input and a pull down signal input of the plurality of gate drivers in a selected area of the liquid crystal display panel, simultaneously; inputting a start pulse into start pulse inputs of the gate drivers to enable the gate lines in the selected area so as to turn on the pixels simultaneously; and outputting a test signal from the plurality of data lines simultaneously. 2. The method of claim 1, wherein the clock inputs in the selected area are connected to a clock testing pad. 3. The method of claim 1, wherein the inverted clock inputs in the selected area are connected to an inverted clock testing pad. 4. The method of claim 1, wherein the pull down inputs in the selected area are connected to a pull down testing pad. 5. The method of claim 1, wherein the start pulse inputs in the selected area are connected to a start pulse testing pad. 6. The method of claim 1, further comprising dividing the plurality of gate lines into a plurality of sub areas within the selected area, wherein the clock signal, the inverted clock signal, the pull down signal and the start pulse signal are inputted into each sub areas in a sequence. 7. The method of claim 6, wherein the clock inputs in the sub areas are connected to a clock testing pad. 8. The method of claim 6, wherein the inverted clock inputs in the sub areas are connected to an inverted clock testing pad. 9. The method of claim 6, wherein the pull down inputs in the sub areas are connected to a pull down testing pad. 10. The method of claim 6, wherein the start pulse inputs in the sub areas are connected to a start pulse testing pad. 11. The method of claim 6, wherein each sub area comprises at least one gate line. 12. The method of claim 6, further comprising testing the divided sub areas by inputting the pull down signal into a plurality of gate drivers in the non-testing sub areas to disable the pixels in the non-testing sub areas and allowing the desired testing sub areas to undergo testing, wherein the pixels in the desired testing sub areas are turned on by the start pulse. 13. The method of claim 6, wherein the sequence is starting from the top of the panel to down, from the bottom of the panel to up, or from both the top and the bottom of the panel towards the center of the panel. 14. The method of claim 6, wherein the start pulse testing pads, the clock signal testing pads, the inverted clock signal testing pads, and the pull down signal testing pads are all electrically disconnected. 15. The method of claim 14, further comprising electrically reconnecting the start pulse testing pads, the clock signal testing pads, the inverted clock signal testing pads, and the pull down signal testing pads after completion of the testing. 16. The method of claim 14, wherein electrically disconnecting the testing pads in every sub area comprises forming a metal oxide semiconductor junction electrically connected between two start pulse testing pads, two clock signal testing pads, two inverted clock signal testing pads, and two pull down signal testing pads. 17. The method of claim 14, wherein electrically disconnecting the testing pads in every sub area comprises forming a soldering junction electrically connected between two start pulse testing pads, two clock signal testing pads, two inverted clock signal testing pads, and two pull down signal testing pads. 18. The method of claim 15, wherein electrically reconnecting comprises applying a voltage to the start pulse testing pads, the clock signal testing pads, the inverted clock signal testing pads, and the pull down signal testing pads, to punch through the metal oxide semiconductor junctions. 19. The method of claim 15, wherein electrically reconnecting comprises applying solder to the start pulse testing pads, the clock signal testing pads, the inverted clock signal testing pads, and the pull down signal testing pads, to solder connect the soldering junctions.
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