초록 ▼

The present invention provides a new baseband integrated circuit (IC) architecture for direct sequence spread spectrum (DSSS) communication receivers. The baseband IC has a single set of baseband correlators serving all channels in succession. No complex parallel channel hardware is required. A sing

The present invention provides a new baseband integrated circuit (IC) architecture for direct sequence spread spectrum (DSSS) communication receivers. The baseband IC has a single set of baseband correlators serving all channels in succession. No complex parallel channel hardware is required. A single on-chip code Numerically Controlled Oscillator (NCO) drives a pseudorandom number (PN) sequence generator, generates all code sampling frequencies, and is capable of self-correct through feedback from an off-chip processor. A carrier NCO generates corrected local frequencies. These on-chip NCOs generate all the necessary clocks. This architecture advantageously reduces the total hardware necessary for the receiver and the baseband IC thus can be realized with a minimal number of gate count. The invention can accommodate any number of channels in a navigational system such as the Global Positioning System (GPS), GLONASS, WAAS, LAAS, etc. The number of channels can be increased by increasing the circuit clock speed.

대표청구항 ▼

We claim: 1. An integrated circuit (IC) chip, comprising: a single set of on-chip baseband correlators serving all channels of a direct sequence spread spectrum (DSSS) communication receiver, wherein said set of on-chip baseband correlators are assigned to a particular GPS signal at a given time or

We claim: 1. An integrated circuit (IC) chip, comprising: a single set of on-chip baseband correlators serving all channels of a direct sequence spread spectrum (DSSS) communication receiver, wherein said set of on-chip baseband correlators are assigned to a particular GPS signal at a given time or an arbitrary number of different receiver channels; a carrier NCO for generating corrected local frequencies; a set of intermediate frequency (IF) signal mixers in communication with said carrier NCO and coupled to said set of on-chip baseband correlators; and a first memory for storing a plurality of input IF samples on a first-in-first-out (FIFO) basis; wherein said set of on-chip baseband correlators are configured to process said input IF samples M samples at a time, where M represents number of said input IF samples in one PN sequence. 2. The IC chip of claim 1, further comprising: an on-chip code Numerically Controlled Oscillator (NCO) in communication with said set of on-chip baseband correlators; wherein said code NCO drives a pseudorandom number (PN) sequence generator; wherein said code NCO generates all code sampling frequencies; and wherein said code NCO is capable of self-correct through feedback from an off-chip processor. 3. The IC chip of claim 1, further comprising: a volatile memory shared by at least said set of on-chip baseband correlators. 4. The IC chip of claim 3, wherein said volatile memory is a dual-port random access memory (RAM). 5. A method of time-sharing a single set of on-chip baseband correlators, wherein said set of on-chip baseband correlators serves all channels of a direct sequence spread spectrum (DSSS) communication receiver, said method comprising the step of: a) storing a plurality of samples of down-converted frequency signals in a first memory; b) reading said plurality of samples from said first memory on a first-in-first-out (FIFO) basis; c) multiplying said samples with a carrier signal via separate in-phase (I) and quadrature (Q) channel paths to generate two parallel I and Q signals; d) separately correlating said I and Q signals with identical locally generated replica codes; e) performing said correlating step over a fixed time interval for each DSSS signal received; and f) storing correlation results in a second memory. 6. The method according to claim 5, further comprising: repeating steps a)-f) for all available DSSS signals. 7. The method according to claim 6, further comprising: transmitting values stored in said second memory to an off-chip processor for adjusting code Numerically Controlled Oscillator (NCO) and carrier NCO values. 8. The method according to claim 7, wherein said off-chip processor is a Digital Signal Processor (DSP), a Reduced Instruction Set Computation (RSIC) processor, or an Application Specific Integrated Circuit (ASIC). 9. A direct sequence spread spectrum (DSSS) communication receiver, comprising: an integrated circuit (IC) chip having a single set of on-chip baseband correlators serving all channels of said direct sequence spread spectrum (DSSS) communication receiver; an on-chip code Numerically Controlled Oscillator (NCO) in communication with said set of on-chip baseband correlators; wherein said code NCO drives a pseudorandom number (PN) sequence generator; said code NCO generates all code sampling frequencies; and said code NCO is capable of self-correct through feedback from an off-chip processor; a carrier NCO for generating corrected local frequencies; and a first memory for storing a plurality of input IF samples on a first-in-first-out (FIFO) basis; wherein said set of on-chip baseband correlators are configured to process said input IF samples M samples at a time, where M represents number of said input IF samples in one PN sequence. 10. The DSSS communication receiver of claim 9, wherein said DSSS communication receiver is a Global Position System (GPS) receiver, a Global'naya Navigatsionnaya Sputnikovaya Sistema (GLONASS) receiver, an European satellite navigation system (GALILEO) receiver, a wide area augmentation system (WAAS), a local area augmentation system (LAAS), or a hybrid thereof. 11. The DSSS communication receiver of claim 10, wherein said set of on-chip baseband correlators are assigned to a particular GPS signal at a given time or an arbitrary number of different receiver channels. 12. The DSSS communication receiver of claim 9, further comprising: a set of intermediate frequency (IF) signal mixers in communication with said carrier NCO and coupled to said set of on-chip baseband correlators. 13. The DSSS communication receiver of claim 9, further comprising: a dual-port random access memory (RAM) shared by at least said set of on-chip baseband correlators.