IPC분류정보
국가/구분 |
United States(US) Patent
등록
|
국제특허분류(IPC7판) |
|
출원번호 |
US-0554128
(2006-10-30)
|
등록번호 |
US-7430146
(2008-09-30)
|
우선권정보 |
JP-2003-415184(2003-12-12) |
발명자
/ 주소 |
- Shionoiri,Yutaka
- Atsumi,Tomoaki
- Kato,Kiyoshi
|
출원인 / 주소 |
- Semiconductor Energy Laboratory Co., Ltd.
|
대리인 / 주소 |
|
인용정보 |
피인용 횟수 :
9 인용 특허 :
28 |
초록
▼
The semiconductor device in which reading and writing of data can be accurately performed by preventing malfunction even when a selection of address delays. The semiconductor device has three factors of a data holding unit, a precharge unit and a delay unit. The data holding unit includes a pluralit
The semiconductor device in which reading and writing of data can be accurately performed by preventing malfunction even when a selection of address delays. The semiconductor device has three factors of a data holding unit, a precharge unit and a delay unit. The data holding unit includes a plurality of memory cells. The precharge unit includes a precharge potential line, a precharge signal line and a plurality of switches. The delay unit includes a plurality of transistors. In addition, it has one or both of an address selecting unit having a column-decoder and a row-decoder and a display unit having a plurality of pixels, as well as the three factors.
대표청구항
▼
What is claimed is: 1. A semiconductor device comprising: an antenna formed on a first substrate; an IC chip formed on a second substrate and mounted on the first substrate, the IC chip comprising: a memory unit having a first thin film transistor, the memory unit comprising: a data holding unit ha
What is claimed is: 1. A semiconductor device comprising: an antenna formed on a first substrate; an IC chip formed on a second substrate and mounted on the first substrate, the IC chip comprising: a memory unit having a first thin film transistor, the memory unit comprising: a data holding unit having a plurality of memory cells; and an address selecting unit comprising: a column-decoder; and a row decoder; a control unit having a second thin film transistor formed on the second substrate, the control unit configured to control the memory unit; and a power generation unit having a third thin film transistor formed on the second substrate, the power generation unit configured to supply a power to the memory unit and the control unit. 2. The semiconductor device according to claim 1, wherein the IC chip is sandwiched between the first substrate and the second substrate. 3. The semiconductor device according to claim 1, wherein the first substrate and the second substrate comprise a resin material. 4. The semiconductor device according to claim 1, wherein the control unit comprises a CPU. 5. The semiconductor device according to claim 1, wherein the data holding unit comprises a read only memory. 6. The semiconductor device according to claim 1, wherein the data holding unit comprises a random access memory. 7. A semiconductor device comprising: an antenna formed on a substrate; an IC chip formed on the substrate, the IC chip comprising: a memory unit having a first thin film transistor, the memory unit comprising: a data holding unit having a plurality of memory cells; and an address selecting unit comprising: a column-decoder; and a row decoder; a control unit having a second thin film transistor formed on the substrate, the control unit configured to control the memory unit; and a power generation unit having a third thin film transistor formed on the substrate, the power generation unit configured to supply a power to the memory unit and the control unit. 8. The semiconductor device according to claim 7, wherein the substrate comprises a resin material. 9. The semiconductor device according to claim 7, wherein the control unit comprises a CPU. 10. The semiconductor device according to claim 7, wherein the data holding unit comprises a read only memory. 11. The semiconductor device according to claim 7, wherein the data holding unit comprises a random access memory. 12. A semiconductor device comprising: an antenna formed on a first substrate; an IC chip formed on a second substrate and mounted on the first substrate, the IC chip comprising: a memory unit having a first thin film transistor, the memory unit comprising: a data holding unit having a plurality of memory cells; an address selecting unit comprising: a column-decoder; and a row decoder; a precharge unit electrically connected to the data holding unit, comprising: a precharge potential line; a plurality of switches electrically connected to the precharge potential line; and a precharge signal line electrically connected to the plurality of switches; and a delay unit electrically connected to the precharge signal line; a control unit having a second thin film transistor formed on the second substrate, the control unit configured to control the memory unit; and a power generation unit having a third thin film transistor formed on the second substrate, the power generation unit configured to supply a power to the memory unit and the control unit. 13. The semiconductor device according to claim 12, wherein the IC chip is sandwiched between the first substrate and the second substrate. 14. The semiconductor device according to claim 12, wherein the first substrate and the second substrate comprise a resin material. 15. The semiconductor device according to claim 12, wherein the control unit comprises a CPU. 16. The semiconductor device according to claim 12, wherein the data holding unit comprises a read only memory. 17. The semiconductor device according to claim 12, wherein the data holding unit comprises a random access memory. 18. The semiconductor device according to claim 12, wherein the delay unit comprises a inverter. 19. A semiconductor device comprising: an antenna formed on a substrate; an IC chip formed on the substrate, the IC chip comprising: a memory unit having a first thin film transistor, the memory unit comprising: a data holding unit having a plurality of memory cells; an address selecting unit comprising: a column-decoder; and a row decoder; a precharge unit electrically connected to the data holding unit, comprising: a precharge potential line; a plurality of switches electrically connected to the precharge potential line; and a precharge signal line electrically connected to the plurality of switches; and a delay unit electrically connected to the precharge signal line; a control unit having a second thin film transistor formed on the substrate, the control unit configured to control the memory unit; and a power generation unit having a third thin film transistor formed on the substrate, the power generation unit configured to supply a power to the memory unit and the control unit. 20. The semiconductor device according to claim 19, wherein the substrate comprises a resin material. 21. The semiconductor device according to claim 19, wherein the control unit comprises a CPU. 22. The semiconductor device according to claim 19, wherein the data holding unit comprises a read only memory. 23. The semiconductor device according to claim 19, wherein the data holding unit comprises a random access memory. 24. The semiconductor device according to claim 19, wherein the delay unit comprises a inverter.
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