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Processing architecture for a reconfigurable arithmetic node

IPC분류정보
국가/구분 United States(US) Patent 등록
국제특허분류(IPC7판)
  • G06F-017/14
출원번호 US-0443596 (2003-05-21)
등록번호 US-7433909 (2008-10-07)
발명자 / 주소
  • Scheuermann,W. James
출원인 / 주소
  • NVIDIA Corporation
대리인 / 주소
    Patterson & Sheridan, L.L.P.
인용정보 피인용 횟수 : 18  인용 특허 : 44

초록

A computational unit, or node, in a adaptable computing system is described. A preferred embodiment of the node allows the node to be adapted for use for any of ten types of functionality by using a combination of execution units with a configurable interconnection scheme. Functionality types inclu

대표청구항

What is claimed is: 1. A reconfigurable arithmetic node (RAN) in an adaptive computing system configurable to execute any one of a plurality of target algorithms, wherein the target algorithms include an Asymmetric FIR filter, a Symmetric FIR Filter, a Complex Multiply FIR Filter, a Sum-of-absolute

이 특허에 인용된 특허 (44)

  1. David Lee TW; Cheng-Wang Huang TW, Apparatus and method for serial data communication between plurality of chips in a chip set.
  2. Robert Fu ; David D. Eaton ; Kevin K. Yee ; Andrew K. Chan, Architecture for field programmable gate array.
  3. Estes Mark D., Associative network method and apparatus.
  4. Martin Bryan R. ; Barraclough Keith, Communication interface between remote transmission of both compressed video and other data and data exchange with local peripherals.
  5. Brian C. Faith ; Thomas Oelsner GB; Gary N. Lai, Configurable computational unit embedded in a programmable device.
  6. Popli Sanjay (Sunnyvale CA) Pickett Scott (Los Gatos CA) Hawley David (Belmont CA) Moni Shankar (Santa Clara CA) Camarota Rafael C. (San Jose CA), Configuration features in a configurable logic array.
  7. Segal, Oren; Avital, Yaniv; Moshe, Moshe; Reshef, Ehud, Data transfer scheme in a communications system incorporating multiple processing elements.
  8. Wittig Ralph D. ; Mohan Sundararajarao ; Carberry Richard A., FPGA configurable logic block with multi-purpose logic/memory circuit.
  9. Trimberger Stephen M., Field programmable gate array having programming instructions in the configuration bitstream.
  10. Law Edwin S. ; Buch Kiran B. ; Baxter Glenn A. ; Pang Raymond C., Hardwire logic device emulating an FPGA.
  11. Stephen L. Wasson, Heterogeneous programmable gate array.
  12. Tavana Danesh ; Yee Wilson K. ; Trimberger Stephen M., Integrated circuit with field programmable and application specific logic areas.
  13. Warren, Robert, Integrated circuit with multiple processing cores.
  14. Cooke Laurence H. ; Phillips Christopher E. ; Wong Dale, Integrated processor and programmable data path chip for reconfigurable computing.
  15. Wong Dale ; Phillips Christopher E. ; Cooke Laurence H., Integrated processor and programmable data path chip for reconfigurable computing.
  16. DeHon Andre ; Mirsky Ethan ; Knight ; Jr. Thomas F., Intermediate-grain reconfigurable processing device.
  17. Wolrich, Gilbert; Bernstein, Debra; Cutter, Daniel; Dolan, Christopher; Adiletta, Matthew J., Mapping requests from a processing unit that uses memory-mapped input-output space.
  18. Master Paul L. ; Hatley William T. ; Scheuermann II Walter J. ; Goodman Margaret J., Method and apparatus for adaptable digital protocol processing.
  19. Cummings Mark R., Method and apparatus for communicating information.
  20. Krein William Todd ; Flaig Charles M. ; Kelly James D., Method and apparatus for dynamic buffer allocation in a bus bridge for pipelined reads.
  21. Bertolet Allan Robert ; Clinton Kim P.N. ; Gould Scott Whitney ; Keyser III Frank Ray ; Reny Timothy Shawn ; Zittritsch Terrance John, Method and system for layout and schematic generation for heterogeneous arrays.
  22. Cooke Laurence H. ; Phillips Christopher E. ; Wong Dale, Method for compiling high level programming languages into an integrated processor with reconfigurable logic.
  23. Harrison David A. ; Silver Joshua M. ; Soe Soren T., Method for programming complex PLD having more than one function block type.
  24. Carter William S. (Santa Clara CA), Microprocessor oriented configurable logic element.
  25. Leung Wu-Hon F. (Downers Grove IL) Morgan Michael J. (Warrenville IL) Tu Shi-Chuan (Lisle IL), Multi-media virtual circuit.
  26. Schunk, Richard; Young, Desmond, Multi-service network switch with quality of access.
  27. Pannell, Donald Robert, Network switch with head of line input buffer queue clearing.
  28. Yamamoto Mitsuru,JPX ; Mashimo Hiroshi,JPX, Network system and terminal apparatus.
  29. Mar, Monte, Programmable analog system architecture.
  30. Camarota Rafael C. (San Jose CA) Furtek Frederick C. (Menlo Park CA) Ho Walford W. (Saratoga CA) Browder Edward H. (Saratoga CA), Programmable logic cell and array.
  31. Camarota Rafael C. (San Jose CA) Furtek Frederick C. (Menlo Park CA) Ho Walford W. (Saratoga CA) Browder Edward H. (Saratoga CA), Programmable logic cell and array with bus repeaters.
  32. Trimberger Stephen M. ; Carberry Richard A. ; Johnson Robert Anders ; Wong Jennifer, Programmable logic device including configuration data or user data memory slices.
  33. Katsutoshi Ito JP, Radio communication apparatus employing a rake receiver.
  34. Ebeling William Henry Carl ; Cronquist Darren Charles ; Franklin Paul David, Reconfigurable computing architecture for providing pipelined data paths.
  35. Alan David Marshall GB; Anthony Stansfield GB; Jean Vuillemin FR, Reconfigurable processor devices.
  36. Knutson Paul G. (Indianapolis IN), Reconfigurable programmable digital filter architecture useful in communication receiver.
  37. Trimberger Stephen M., Reprogrammable instruction set accelerator.
  38. Kelleher Brian M. ; Dewey Thomas E., Scalable graphics processor architecture.
  39. Kopp Randall L. (Irvine CA) Johnson S. Val (Anaheim CA), Single-chip self-configurable parallel processor.
  40. Iadanza Joseph Andrew (Hinesburg VT), System and method for dynamically reconfiguring a programmable gate array.
  41. Davis Donald J. ; Bennett Toby D. ; Harris Jonathan C. ; Miller Ian D. ; Edwards Stephen G., System and method for programming the hardware of field programmable gate arrays (FPGAs) and related reconfiguration resources as if they were software by creating hardware objects.
  42. Furtek Frederick C. (Menlo Park CA) Camarota Rafael C. (San Jose CA), Versatile programmable logic cell for use in configurable logic arrays.
  43. Agrawal Prathima ; Cravatts Mark Robert ; Trotter John Andrew ; Srivastava Mani Bhushan, Wireless adapter architecture for mobile computing.
  44. Athanas Peter ; Bittner ; Jr. Ray A., Worm-hole run-time reconfigurable processor field programmable gate array (FPGA).

이 특허를 인용한 특허 (18)

  1. Ching, Alvin Y.; Wong, Jennifer; New, Bernard J.; Simkins, James M.; Thendean, John M.; Wong, Anna Wing Wah; Vadi, Vasisht Mantra, Architectural floorplan for a digital signal processing circuit.
  2. Wong, Anna Wing Wah; Wong, Jennifer; New, Bernard J.; Ching, Alvin Y.; Thendean, John M.; Simkins, James M.; Vadi, Vasisht Mantra; Schultz, David P., Arithmetic logic unit circuit.
  3. Scheuermann, W. James; Hogenauer, Eugene B., Control node for multi-core system.
  4. New, Bernard J.; Vadi, Vasisht Mantra; Wong, Jennifer; Ching, Alvin Y.; Thendean, John M.; Wong, Anna Wing Wah; Simkins, James M., Digital signal processing block having a wide multiplexer.
  5. Simkins, James M.; Ching, Alvin Y.; Thendean, John M.; Vadi, Vasisht M.; Poon, Chi Fung; Rab, Muhammad Asim, Digital signal processing block with preadder stage.
  6. Simkins, James M.; Wong, Jennifer; New, Bernard J.; Ching, Alvin Y.; Thendean, John M.; Wong, Anna Wing Wah; Vadi, Vasisht Mantra, Digital signal processing circuit having a SIMD circuit.
  7. Vadi, Vasisht Mantra; Wong, Jennifer; New, Bernard J.; Ching, Alvin Y.; Thendean, John M.; Wong, Anna Wing Wah; Simkins, James M., Digital signal processing circuit having a pattern circuit for determining termination conditions.
  8. Vadi, Vasisht Mantra; Wong, Jennifer; New, Bernard J.; Ching, Alvin Y.; Thendean, John M.; Wong, Anna Wing Wah; Simkins, James M., Digital signal processing circuit having a pattern detector circuit.
  9. New, Bernard J.; Wong, Jennifer; Simkins, James M.; Ching, Alvin Y.; Thendean, John M.; Wong, Anna Wing Wah; Vadi, Vasisht Mantra, Digital signal processing circuit having a pattern detector circuit for convergent rounding.
  10. Simkins, James M.; Thendean, John M.; Vadi, Vasisht Mantra; New, Bernard J.; Wong, Jennifer; Wong, Anna Wing Wah; Ching, Alvin Y., Digital signal processing circuit having a pre-adder circuit.
  11. Thendean, John M.; Wong, Jennifer; New, Bernard J.; Ching, Alvin Y.; Simkins, James M.; Wong, Anna Wing Wah; Vadi, Vasisht Mantra, Digital signal processing circuit having an adder circuit with carry-outs.
  12. Simkins, James M.; Wong, Jennifer; New, Bernard J.; Ching, Alvin Y.; Thendean, John M.; Wong, Anna Wing Wah; Vadi, Vasisht Mantra, Digital signal processing circuit having input register blocks.
  13. Simkins, James M.; Wong, Jennifer; New, Bernard J.; Ching, Alvin Y.; Thendean, John M.; Wong, Anna Wing Wah; Vadi, Vasisht Mantra; Schultz, David P., Digital signal processing element having an arithmetic logic unit.
  14. Sutou, Shin-ichi, Dynamic reconfigurable circuit with a plurality of processing elements, data network, configuration memory, and immediate value network.
  15. Scheuermann, W. James; Hogenauer, Eugene B., Hardware task manager.
  16. Scheuermann, W. James; Hogenauer, Eugene B., Hardware task manager.
  17. Tinker, Darrell E.; Heragu, Keerthinarayan, High performance implementation of the FFT butterfly computation.
  18. Wendling, Xavier; Simkins, James M., Method of and circuit for implementing a filter in an integrated circuit.
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