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A programmable after-package, on-chip reference voltage trim circuit for an integrated circuit having a plurality of programmable trim cells generating a programmed sequence. A converter is provided to convert the bit sequence into a trim current. The trim current is added to an initial value of a r

A programmable after-package, on-chip reference voltage trim circuit for an integrated circuit having a plurality of programmable trim cells generating a programmed sequence. A converter is provided to convert the bit sequence into a trim current. The trim current is added to an initial value of a reference voltage to be trimmed, as generated by the integrated circuit. Once the correct value of the trim current is determined, isolation circuitry is programmed to isolate the trim circuitry from the remainder of the IC, thereby freeing the logic and package pins associated with the IC for use by users of the IC. The preferred trim circuitry includes fuses which are blown in accordance with a bit value supplied to the trim cell to permanently fix a trim current value, once a best fit value is determined.

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What is claimed is: 1. An integrated circuit (IC) comprising: a plurality of pins; and an after package trim circuit configured to control at least one of said plurality of pins during a first time interval to trim an element of said IC, said after package trim circuit further configured to relinqu

What is claimed is: 1. An integrated circuit (IC) comprising: a plurality of pins; and an after package trim circuit configured to control at least one of said plurality of pins during a first time interval to trim an element of said IC, said after package trim circuit further configured to relinquish said at least one of said plurality of pins after said first time interval such that said at least one of said plurality of pins is configured to actively perform a first function, wherein said first function is different from said trimming of said element of said IC. 2. The IC of claim 1, wherein said at least one pin receives a common voltage signal during said first time interval. 3. The IC of claim 1, wherein said after package trim circuit generates a trim voltage signal to add to an initial voltage reference signal generated by said IC. 4. The IC of claim 3, wherein said after package trim circuit comprises: an after-package trim cell circuit array configured to provide a digital signal representative of a test signal; and an output decision circuit configured to receive said digital signal and provide an analog voltage reference signal at an output pin of said IC, said analog voltage reference signal equal to said trim voltage signal plus said initial voltage reference signal. 5. The IC of claim 1, wherein a type of said IC is selected from the group consisting of D/A converter circuits, A/D converter circuits, Op Amps, or VCO circuits, wherein said second function is based on said type of IC. 6. The IC of claim 1, wherein said IC comprises a register being controlled to generate a sequence of test bit signal and a sequence of set bit signals; a plurality of after package programmable trim cell circuits selectively coupled to said register, each said cell receiving a test bit signal and set bit signal from said register, said after package trim cells being configured to generate an output signal equal to said test bit signal or said set bit signal, respectively, supplied to each after package trim cell; a digital to analog converter (DAC) circuit coupled to said output signals and configured to generate a trim current signal proportional to said output signals; and a resistor configured to convert said trim current into a trim voltage signal, said trim voltage being added to an initial value of a reference voltage generated by said IC. 7. The IC of claim 6, wherein said test signal comprises a sequential binary signal. 8. An integrated circuit (IC) comprising: a plurality of pins, wherein at least one of said plurality of pins is configured to perform a first and at least a second function, wherein said second function is different from said first function; and an after package trim circuit configured to selectively control said at least one of said plurality of pins to perform said first function during a first time interval and said second function after said first time interval, wherein said first function comprises trimming an element of said IC. 9. The IC of claim 8, wherein said after package trim circuit is configured to relinquish said at least one of said plurality of pins after said first time interval such that said at least one of said plurality of pins is configured to perform said second function. 10. The IC of claim 9, wherein said after package trim circuit comprises a plurality of after package trim cell circuits, wherein said after package trim circuit is configured to assign bit values to said plurality of after package trim cell circuits to trim said element of said IC. 11. The IC of claim 10, wherein said after package trim circuit is configured to permanently assign bit values to said plurality of after package trim cell circuits to trim said element of said IC. 12. The IC of claim 8, wherein a type of said IC is selected from the group consisting of D/A converter circuits, A/D converter circuits, Op Amps, or VCO circuits, wherein said second function is based on said type of IC. 13. The IC of claim 8, wherein said at least one pin receives a common voltage signal during said first time interval. 14. The IC of claim 8, wherein said after package trim circuit generates a trim voltage signal to add to an initial voltage reference signal generated by said IC. 15. A method comprising: during a first time interval, trimming an element of an integrated circuit (IC) utilizing at least one of a plurality of pins of said IC; and after said first time interval, releasing said at least one of said plurality of pins and actively utilizing said at least one of a plurality of pins to actively perform a function other than said trimming operation. 16. The method of claim 15, wherein said pin receives a common voltage signal during said trimming operation. 17. The method of claim 15, wherein said element comprises a reference voltage level. 18. The method of claim 15, wherein said trimming operation comprises: generating a binary test signal sequence; generating a trim current representative of said binary test signal sequence at an output terminal; generating a trim voltage from a resistive element coupled to said output terminal; adding said trim voltage to a reference voltage to obtain a sum; determining if said sum is within a predetermined range of a high precision reference signal; and fixing said trim voltage if said sum is within said predetermined range. 19. The method of claim 15, wherein fixing said trim voltage further comprises permanently setting said binary sequence at a value that generates said trim voltage resulting in said sum within said predetermined range.