IPC분류정보
국가/구분 |
United States(US) Patent
등록
|
국제특허분류(IPC7판) |
|
출원번호 |
US-0878218
(2004-06-28)
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등록번호 |
US-7436227
(2008-10-14)
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발명자
/ 주소 |
- Thomsen,Axel
- Huang,Yunteng
- Hein,Jerrell P.
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출원인 / 주소 |
- Silicon Laboratories Inc.
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대리인 / 주소 |
Zagorin O'Brien Graham LLP
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인용정보 |
피인용 횟수 :
24 인용 특허 :
87 |
초록
▼
A first phase-locked loop (PLL) circuit includes an input for receiving a timing reference signal from an oscillator, a controllable oscillator circuit supplying an oscillator output signal, and a multi-modulus feedback divider circuit. A second control loop circuit is selectably coupled through a s
A first phase-locked loop (PLL) circuit includes an input for receiving a timing reference signal from an oscillator, a controllable oscillator circuit supplying an oscillator output signal, and a multi-modulus feedback divider circuit. A second control loop circuit is selectably coupled through a select circuit to supply a digital control value (M) to the multi-modulus feedback divider circuit of the first loop circuit to thereby control the oscillator output signal. While the second control loop is coupled to supply the control value to the feedback divider circuit, the control value is determined according to a detected difference between the oscillator output signal and a reference signal coupled to the second control loop circuit at a divider circuit. While the second control loop circuit is not coupled to control the first PLL circuit, the first PLL circuit receives a digital control value to control a divide ratio of the feedback divider, the digital control value is determined at least in part according to a stored control value stored in nonvolatile storage, the stored control value corresponding to a desired frequency of the oscillator output signal.
대표청구항
▼
What is claimed is: 1. An apparatus comprising: a phase-locked loop (PLL) circuit including an input for receiving a timing reference signal, a controllable oscillator circuit, and a feedback divider circuit; a control loop circuit configured to be selectively coupled to supply a control value to t
What is claimed is: 1. An apparatus comprising: a phase-locked loop (PLL) circuit including an input for receiving a timing reference signal, a controllable oscillator circuit, and a feedback divider circuit; a control loop circuit configured to be selectively coupled to supply a control value to the feedback divider circuit to thereby control the oscillator output signal; a nonvolatile storage; wherein while the control loop circuit is not coupled to control the PLL circuit, the PLL circuit is coupled to receive a digital control value as the control value to control a divide ratio of the feedback divider, the digital control value being determined at least in part according to a stored control value stored in the nonvolatile storage, the stored control value corresponding to a desired frequency of the oscillator output signal; and wherein, while the control loop circuit is coupled to supply the control value to the feedback divider circuit, the control value is determined according to a detected difference between a feedback signal coupled to the oscillator circuit and a reference signal coupled to an input of the control loop circuit. 2. The apparatus as recited in claim 1 wherein the control value supplied is a digital control value. 3. The apparatus as recited in claim 1 wherein the apparatus is an integrated circuit. 4. The apparatus as recited in claim 1 wherein the feedback divider circuit is a multi-modulus feedback divider circuit. 5. The apparatus as recited in claim 1 further comprising: a temperature compensation circuit coupled to supply an adjustment value according to a detected temperature, and wherein the control value supplied to the feedback divider circuit is adjusted according to the adjustment value, while the control loop circuit is not coupled to supply the control value to the feedback divider circuit. 6. The apparatus as recited in claim 1 further comprising a voltage control input to adjust a frequency of the oscillator output signal and wherein the control value supplied to the divider circuit is adjusted according to a voltage value present on the voltage control input. 7. The apparatus as recited in claim 1 further comprising a resonator supplying the timing reference signal. 8. The apparatus as recited in claim 7 wherein the resonator is one of a crystal oscillator and a surface acoustic wave (SAW) resonator. 9. The apparatus as recited in claim 1 wherein the control loop circuit is a phase-locked loop. 10. An apparatus comprising: a phase-locked loop (PLL) circuit including an input for receiving a timing reference signal, a controllable oscillator circuit, and a feedback divider circuit; a control loop circuit configured to be selectively coupled to supply a control value to the feedback divider circuit to thereby control the oscillator output signal; a nonvolatile storage; wherein while the control loop circuit is not coupled to control the PLL circuit, the PLL circuit is coupled to receive a digital control value as the control value to control a divide ratio of the feedback divider, the digital control value being determined at least in part according to a stored control value stored in the nonvolatile storage, the stored control value corresponding to a desired frequency of the oscillator output signal; and wherein the stored control value in the non-volatile storage is based on a digital control value that was stored as a result of the control loop circuit detecting a lock condition indicating a signal coupled to an output of the oscillator circuit was locked to a reference signal coupled to an input of the control loop circuit. 11. An apparatus comprising: a phase-locked loop (PLL) circuit including an input for receiving a timing reference signal, a controllable oscillator circuit, and a feedback divider circuit; a control loop circuit configured to be selectively coupled to supply a control value to the feedback divider circuit to thereby control the oscillator output signal; a nonvolatile storage; wherein while the control loop circuit is not coupled to control the PLL circuit, the PLL circuit is coupled to receive a digital control value as the control value to control a divide ratio of the feedback divider, the digital control value being determined at least in part according to a stored control value stored in the nonvolatile storage, the stored control value corresponding to a desired frequency of the oscillator output signal; and wherein the control loop circuit is implemented as a low bandwidth phase-locked loop and a bandwidth of the PLL circuit is substantially higher than the low bandwidth of the control loop circuit. 12. The apparatus as recited in claim 11 wherein the low bandwidth phase-locked loop has a bandwidth less than or equal to approximately 1 KHz and the substantially higher bandwidth of the PLL circuit is between approximately 10 KHz and 10 MHz. 13. A method comprising: selectively coupling an inner loop circuit to have its output frequency determined, at least in part, by one of a first control value supplied by an outer loop circuit and a second control value corresponding to a stored control value in a nonvolatile storage; and supplying the selectively coupled one of the first and second control values as a control value to control a divide ratio of a feedback divider circuit of the inner loop circuit; wherein the method further comprises operating the outer loop circuit as a low bandwidth phase-locked loop and operating the inner loop circuit as a phase-locked loop having a substantially higher bandwidth than a bandwidth of the outer loop circuit. 14. The method as recited in claim 13 comprising: supplying the inner loop with a timing reference signal from one of a crystal oscillator and a surface acoustic wave (SAW) device as an input into the inner loop circuit. 15. The method as recited in claim 14 wherein the inner loop circuit is a fractional N loop such that a period of the timing reference signal may be a non-integer multiple of a period of an output signal generated by the inner loop circuit. 16. The method as recited in claim 13 further comprising supplying a stream of integers from a delta sigma modulator corresponding to the control value to control the divide ratio of the feedback divider. 17. The method as recited in claim 13 further comprising determining the control value supplied to the inner loop circuit to control the divide ratio at least in part according to a detected temperature. 18. The method as recited in claim 13 further comprising determining the control value supplied to the inner loop circuit to control the divide ratio at least in part according to a control voltage supplied on a voltage control input terminal to adjust the output frequency of the inner loop circuit. 19. An integrated circuit comprising: a first phase-locked loop (PLL) circuit including an input for receiving a timing reference signal, a controllable oscillator circuit, and a feedback divider circuit; a non-volatile memory storing a stored value corresponding to a desired frequency of an output signal of the controllable oscillator circuit; a second phase-locked loop circuit including a phase detector; a selector circuit having inputs coupled to the phase detector of the second phase-locked loop circuit and to a control signal corresponding to the stored value in the nonvolatile memory, the selector circuit being coupled to provide a divider control signal to the feedback divider circuit. 20. An apparatus comprising: a phase-locked loop (PLL) circuit including an input for receiving a timing reference signal, a controllable oscillator circuit, and a feedback divider circuit; and a control ioop circuit configured to be selectively coupled to suppiy a control value to the feedback divider circuit to thereby control the oscillator output signal; wherein the control loop circuit is selectively coupled though a selector circuit; and wherein the selector circuit is coupled to select between the control value supplied by the control loop circuit and another control value corresponding to a desired output frequency of the phase-locked loop stored in a non-volatile memory; and wherein the control loop circuit comprises a phase detector and the control value supplied by the control loop circuit corresponds to an indication from the phase detector of a difference between an output from the phase-locked loop circuit and a timing reference signal. 21. An apparatus comprising: a fractional N inner loop circuit including, an input for receiving a timing reference signal; a feedback divider circuit; and a controllable oscillator circuit; an outer loop circuit coupled to compare a feedback signal coupled to an output of the oscillator circuit and a reference signal coupled to an input of the outer loop circuit, and to generate an error signal indicative of the comparison; and wherein the outer loop circuit is coupled to supply a divider control signal to control a divide ratio of the feedback divider circuit, the divider control signal being determined at least in part according to the error signal generated by the outer loop circuit; and wherein the outer loop circuit has a bandwidth substantially lower than a bandwidth of the inner loop circuit. 22. The apparatus as recited in claim 21 wherein a desired output frequency is specified as a multiple of the reference clock signal. 23. The apparatus as recited in claim 21 further comprising a divider circuit coupled to the input of the outer loop circuit and coupled to supply the reference signal for comparison. 24. The apparatus as recited in claim 21 further comprising one of a crystal oscillator and a surface acoustic wave (SAW) resonator supplying the timing reference signal. 25. The apparatus as recited in claim 21 wherein the inner and outer loop circuits are phase-locked loops, each including a digital loop filter. 26. The apparatus as recited in claim 21 wherein the apparatus is an integrated circuit. 27. The apparatus as recited in claim 21 wherein the reference signal and the timing reference signal are coupled to a common source. 28. The apparatus as recited in claim 21 wherein the bandwidth of the outer loop circuit is less than or equal to approximately 1 KHz and the bandwidty of the inner loop circuit is between approximately 10 KHz and 10 MHz. 29. A method comprising: receiving a first reference signal as an input to a first phase-locked loop (PLL) circuit; generating an error signal in a second phase-locked loop indicative of a difference between a feedback signal coupled to an output of the first PLL circuit and a second reference signal coupled to an input of the second phase-locked loop, the second PLL circuit being a low bandwidth PLL; and supplying a control signal, based at least in part on the error signal, to control a divider circuit in a feedback path of the first PLL circuit; and operating the first PLL circuit with a substantially higher bandwidth than the second PLL circuit. 30. The method as recited in claim 29 wherein the control signal supplied is a digital signal. 31. The method as recited in claim 29 further comprising controlling the first PLL circuit output signal to be a desired multiple of the reference clock signal through programmable divider values. 32. The method as recited in claim 29 further comprising supplying the timing reference signal from one of a crystal oscillator and a surface acoustic wave (SAW) device.
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