이 특허에 인용된 특허 (285)

1. Lung Hsing Lan,TWX ; Lu Tao Cheng,TWX ; Wang Mam Tsung,TWX, 8 bit per cell non-volatile semiconductor memory structure utilizing trench technology and dielectric floating gate.

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2. Jack Oon Chu ; Khalid Ezzeldin Ismail, Advance integrated chemical vapor deposition (AICVD) for semiconductor.

   상세보기
3. Chu Jack Oon ; Ismail Khalid Ezzeldin, Advance integrated chemical vapor deposition (AICVD) for semiconductor devices.

   상세보기
4. Kub Francis J. ; Temple Victor ; Hobart Karl ; Neilson John, Advanced methods for making semiconductor devices by low temperature direct bonding.

   상세보기
5. Bean John C. (New Providence NJ) Higashi Gregg S. (Basking Ridge NJ) Hull Robert (South Orange NJ) Peticolas Justin L. (Wescosville PA), Article comprising a lattice-mismatched semiconductor heterostructure.

   상세보기
6. Chu Jack Oon ; Ismail Khalid Ezzeldin ; Lee Kim Yang ; Ott John Albrecht, Bulk and strained silicon on insulator using local selective oxidation.

   상세보기
7. Fitzgerald, Eugene A., Buried channel strained silicon FET using a supply layer created through ion implantation.

   상세보기
8. Fitzgerald, Eugene A., Buried channel strained silicon FET using a supply layer created through ion implantation.

   상세보기
9. Fischer Hermann,DEX ; Hofmann Franz,DEX, CMOS integrated circuit including forming doped wells, a layer of intrinsic silicon, a stressed silicon germanium layer where germanium is between 25 and 50%, and another intrinsic silicon layer.

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10. Matsumoto Koichi,JPX, CMOS semiconductor device having dual-gate electrode construction and method of production of the same.

    상세보기
11. Bradbury Donald R. (Palo Alto CA) Tsao Chi-Wing (Piedmont CA) Kamins Theodore I. (Palo Alto CA), CVD lateral epitaxial growth of silicon over insulators.

    상세보기
12. Murthy Anand ; Chau Robert S., Cobalt salicidation method on a silicon germanium film.

    상세보기
13. Harame David L. (Mohegan Lake NY) Patton Gary L. (Poughkeepsie NY) Stork Maria C. (Yorktown Heights NY), Complementary bipolar transistor structure and method for manufacture.

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14. Wang Kang L. (Santa Monica CA) Woo Jason C. (Encino CA), Complementary field effect transistors having strained superlattice structure.

    상세보기
15. Baca Albert G. (Albuquerque NM) Drummond Timothy J. (Albuquerque NM) Robertson Perry J. (Albuquerque NM) Zipperian Thomas E. (Albuquerque NM), Complementary junction heterostructure field-effect transistor.

    상세보기
16. Yeo, Yee-Chia; Lin, Chun Chieh; Yang, Fu-Liang; Hu, Chen Ming, Complementary metal oxide semiconductor transistor technology using selective epitaxy of a strained silicon germanium layer.

    상세보기
17. Yeo, Yee-Chia; Lin, Chun-Chieh; Yang, Fu-Liang; Hu, Chen Ming, Complementary metal oxide semiconductor transistor technology using selective epitaxy of a strained silicon germanium layer.

    상세보기
18. Ismail Khaled E. (Cairo NY EGX) Stern Frank (Pleasantville NY), Complementary metal-oxide semiconductor transistor logic using strained SI/SIGE heterostructure layers.

    상세보기
19. Robert L. Thornton ; Christopher L. Chua, Compliant substrates for growing lattice mismatched films.

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20. Ohori Tatsuya,JPX, Compound semiconductor device constructed on a heteroepitaxial substrate.

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21. Yokoyama Mitsunori,JPX ; Tanaka Hitoshi,JPX ; Wada Jun,JPX, Compound semiconductor device having a reduced source resistance.

    상세보기
22. Fitzgerald Eugene A., Controlling threading dislocation densities in Ge on Si using graded GeSi layers and planarization.

    상세보기
23. Fitzgerald Eugene A., Controlling threading dislocation densities in Ge on Si using graded GeSi layers and planarization.

    상세보기
24. Horstmann Manfred,DEX ; Wieczorek Karsten,DEX ; Hause Frederick N., Device improvement by source to drain resistance lowering through undersilicidation.

    상세보기
25. Bean Kenneth E. (Richardson TX) Malhi Satwinder S. (Garland TX) Runyan Walter R. (Dallas TX), Discretionary gettering of semiconductor circuits.

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26. Narayan Jagdish (Raleigh NC) Fan John C. C. (Chestnut Hill MA), Dislocation density reduction in gallium arsenide on silicon heterostructures.

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27. Psaras Peter A. (Ossining NY) Tu King-Ning (Chappaqua NY) Thompson Richard D (Lake Peekskill NY), Dopant control of metal silicide formation.

    상세보기
28. Boyanov, Boyan; Doyle, Brian; Kavalieros, Jack; Murthy, Anand; Chau, Robert, Double-gate transistor with enhanced carrier mobility.

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29. Nakatani Mitsunori (Itami JPX), Dual field effect transistor structure employing a single source region.

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30. Harari Eliyahou ; Guterman Daniel C. ; Samachisa George ; Yuan Jack H., Dual floating gate EEPROM cell array with steering gates shared adjacent cells.

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31. Xiang Qi ; Jeon Joong, Dual material gate MOSFET technique.

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32. Tatau Nishinaga JP, ELO semiconductor substrate.

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33. Siang Ping Kwok ; William F. Richardson ; Dirk N. Anderson, Edge stress reduction by noncoincident layers.

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34. Tomioka Yugo (Sagamihara JPX) Iwasa Shoichi (Sagamihara JPX) Sato Yasuo (Sagamihara JPX) Wada Toshio (Sagamihara JPX) Anzai Kenji (Sagamihara JPX), Electrically alterable n-bit per cell non-volatile memory with reference cells.

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35. Moslehi Mehrdad (Los Altos CA), Elevated source/drain junction metal oxide semiconductor field-effect transistor using blanket silicon deposition.

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36. Candelaria Jon J. (Tempe AZ), Enhanced mobility MOSFET device and method.

    상세보기
37. Wu, Kenneth C.; Fitzgerald, Eugene A.; Borenstein, Jeffrey T., Etch stop layer system.

    상세보기
38. Minoru Kubo JP; Katsuya Nozawa JP; Masakatsu Suzuki JP; Takeshi Uenoyama JP; Yasuhito Kumabuchi JP, FET having a Si/SiGeC heterojunction channel.

    상세보기
39. Bin Yu, Fabrication of a wide metal silicide on a narrow polysilicon gate structure.

    상세보기
40. Dennard Robert H. (Peekskill NY) Meyerson Bernard S. (Yorktown Heights NY) Rosenberg Robert (Peekskill NY), Fabrication of defect free silicon on an insulating substrate.

    상세보기
41. Kub Francis J. ; Hobart Karl D., Fabrication ultra-thin bonded semiconductor layers.

    상세보기
42. Wieczorek, Karsten; Stephan, Rolf; Horstmann, Manfred; Kruegel, Stephan, Field effect transistor with an improved gate contact and method of fabricating the same.

    상세보기
43. Oliver G. Schmidt DE; Karl Eberl DE, Field-effect transistor based on embedded cluster structures and process for its production.

    상세보기
44. Mei Shaw-Ning ; Vishnesky Edward J., Flash memory structure with floating gate in vertical trench.

    상세보기
45. Desai Ankur H. ; Vadnais David L. ; Standley Robert W., Flattening process for epitaxial semiconductor wafers.

    상세보기
46. Kencke David L. ; Banerjee Sanjay K., Floating gate transistor having buried strained silicon germanium channel layer.

    상세보기
47. Lee, Minjoo L.; Leitz, Christopher W.; Fitzgerald, Eugene A., Formation of planar strained layers.

    상세보기
48. Fitzgerald, Eugene A.; Hammond, Richard; Currie, Matthew, Gate technology for strained surface channel and strained buried channel MOSFET devices.

    상세보기
49. Hoffman,Thomas; Cea,Stephen M.; Giles,Martin D., Gate-induced strain for MOS performance improvement.

    상세보기
50. Crabbe' Emmanuel ; Meyerson Bernard Steele ; Stork Johannes Maria Cornelis ; Verdonckt-Vandebroek Sophie, Graded channel field effect transistor.

    상세보기
51. Kitahara Kuninori (Zama JPX) Ohtsuka Nobuyuki (Atsugi JPX) Ozeki Masashi (Yokohama JPX), Hetero-epitaxially grown compound semiconductor substrate.

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52. Fitzgerald, Eugene A., Heterointegration of materials using deposition and bonding.

    상세보기
53. Fitzgerald, Eugene A., Heterointegration of materials using deposition and bonding.

    상세보기
54. Fitzgerald, Eugene A., Heterointegration of materials using deposition and bonding.

    상세보기
55. Mori Hideki,JPX ; Gomi Takayuki,JPX, Heterojunction bipolar semiconductor device.

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56. Endo Takahiko (Hino JPX) Katoh Riichi (Yokohama JPX), Heterojunction bipolar transistor.

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57. Fujioka Hiroshi (Tokyo JPX), Heterojunction bipolar transistor.

    상세보기
58. Takagi, Takeshi; Yuki, Koichiro; Toyoda, Kenji; Kanzawa, Yoshihiko, Heterojunction bipolar transistor and method for fabricating the same.

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59. Forbes Leonard ; Noble Wendell P., High density flash memory.

    상세보기
60. Shimomura Hiroshi,JPX ; Hirai Takehiro,JPX ; Hayashi Joji,JPX ; Nakamura Takashi,JPX, High frequency ring gate MOSFET.

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61. Ouyang Qiqing ; Tasch ; Jr. Al F. ; Banerjee Sanjay Kumar, High mobility heterojunction transistor and method.

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62. Anderson, Brent A.; Baie, Xavier; Mann, Randy W.; Nowak, Edward J.; Rankin, Jed H., High mobility transistors in SOI and method for forming.

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63. Chu, Jack Oon, High performance FET devices and methods therefor.

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64. Furukawa Toshiharu ; Ellis-Monaghan John Joseph ; Slinkman James Albert, High resolution dopant/impurity incorporation in semiconductors via a scanned atomic force probe.

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65. Jack Oon Chu ; Richard Hammond ; Khalid EzzEldin Ismail ; Steven John Koester ; Patricia May Mooney ; John A. Ott, High speed composite p-channel Si/SiGe heterostructure for field effect devices.

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66. Brigham Lawrence N. (Beaverton OR) Lee Yung-Huei (Sunnyvale CA) Chau Robert S. (Beaverton OR) Cotner Raymond E. (Beaverton OR), High tensile nitride layer.

    상세보기
67. Wong Chun Chiu D., Highly compact memory device with nonvolatile vertical transistor memory cell.

    상세보기
68. Broekaert Tom P. E., III-V nitride resonant tunneling.

    상세보기
69. Yoshimi Makoto (Tokyo JPX) Inaba Satoshi (Tokyo JPX) Murakoshi Atsushi (Tokyo JPX) Terauchi Mamoru (Tokyo JPX) Shigyo Naoyuki (Tokyo JPX) Matsushita Yoshiaki (Tokyo JPX) Aoki Masami (Tokyo JPX) Hamam, Insulated-gate transistor having narrow-bandgap-source.

    상세보기
70. Lustig Bernhard,DEX ; Schaefer Herbert,DEX ; Franosch Martin,DEX, Integrated CMOS circuit arrangement and method for the manufacture thereof.

    상세보기
71. Violette Katherine E. ; Wise Rick L. ; Ashburn Stanton P. ; Nandakumar Mahalingam ; Grider Douglas T., Integrated circuit isolation.

    상세보기
72. Muller Heinrich G., Inverted layer epitaxial liftoff process.

    상세보기
73. Ma, Qing; Lee, Jin; Fujimoto, Harry; Dai, Changhong; Lee, Shiuh-Wuu; Eiles, Travis; Seshan, Krishna, Isolation structure configurations for modifying stresses in semiconductor devices.

    상세보기
74. Thompson Scott ; Bohr Mark T. ; Packan Paul A., Low damage doping technique for self-aligned source and drain regions.

    상세보기
75. Legoues Francoise Kolmer (Peekskill NY) Meyerson Bernard Steele (Yorktown Heights NY), Low defect density/arbitrary lattice constant heteroepitaxial layers.

    상세보기
76. Bhat Rajaram (Red Bank NJ) Lo Yu-hwa (Ithaca NY), Low-temperature fusion of dissimilar semiconductors.

    상세보기
77. Naem, Abdalla Aly, MOS transistor and method of forming the transistor with a channel region in a layer of composite material.

    상세보기
78. Meyerson Bernard S. (Yorktown Heights NY), Method and apparatus for low temperature, low pressure chemical vapor deposition of epitaxial silicon layers.

    상세보기
79. Henley Francois J. ; Cheung Nathan W., Method for controlled cleaving process.

    상세보기
80. Kub Francis J. ; Hobart Karl D., Method for fabricating singe crystal materials over CMOS devices.

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81. Sohn Dong Kyun,KRX ; Park Ji Soo,KRX ; Bae Jong Uk,KRX, Method for fabricating thin film at high temperature.

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82. Liaw Hang Ming ; Burt Curtis Lee ; Hong Stella Q. ; Stein Clifford P., Method for forming a semiconductor device having a heteroepitaxial layer.

    상세보기
83. Bich-Yen Nguyen ; William J. Taylor, Jr. ; Philip J. Tobin ; David L. O'Meara ; Percy V. Gilbert ; Yeong-Jyh T. Lii ; Victor S. Wang, Method for forming a semiconductor device with an opening in a dielectric layer.

    상세보기
84. Albert Feng-Der Chin TW; Ming-Jang Hwang TW, Method for forming an epitaxial silicon-germanium layer.

    상세보기
85. Pfiester James R. (Austin TX) Kirsch Howard C. (Austin TX), Method for forming isolation regions in a semiconductor device.

    상세보기
86. Lin Kang-Cheng,TWX ; Wu Hong-Woei,TWX, Method for forming metal silicide by laser irradiation.

    상세보기
87. Nakato Tatsuo, Method for forming silicon-germanium/Si/silicon dioxide heterostructure using germanium implant.

    상세보기
88. Liaw Hang M. (Scottsdale AZ) Nguyen Ha T.-T. (Mesa AZ), Method for improved surface planarity in selective epitaxial silicon.

    상세보기
89. Brasen Daniel (Lake Hiawatha NJ) Fitzgerald ; Jr. Eugene A. (Bridgewater NJ) Green Martin L. (New Providence NJ) Xie Ya-Hong (Flemington NJ), Method for making low defect density semiconductor heterostructure and devices made thereby.

    상세보기
90. Selvakumar Chettypalayam R. (Waterloo CAX) Chamberlain Savvas G. (Waterloo CAX), Method for making silicon-germanium devices using germanium implantation.

    상세보기
91. Matsui Masaki,JPX ; Yamauchi Shoichi,JPX ; Ohshima Hisayoshi,JPX ; Onoda Kunihiro,JPX ; Asai Akiyoshi,JPX ; Sasaya Takanari,JPX ; Enya Takeshi,JPX ; Sakakibara Jun,JPX, Method for manufacturing a semiconductor substrate.

    상세보기
92. Nagashima Naoki,JPX, Method for manufacturing semiconductor device.

    상세보기
93. Kibbel Horst,DEX ; Kuchenbecker Jessica,DEX, Method for producing epitaxial silicon germanium layers.

    상세보기
94. Lo Yu-Hwa ; Ejeckam Felix, Method for producing high quality heteroepitaxial growth using stress engineering and innovative substrates.

    상세보기
95. Kant Shree, Method for sizing PMOS pull-up devices.

    상세보기
96. Karapiperis Leonidas (Bourg la Reine FRX) Pribat Didier (Paris FRX), Method for the directed modulation of the composition or doping of semiconductors, notably for the making of planar type.

    상세보기
97. Goesele Ulrich M. ; Tong Q.-Y., Method for the transfer of thin layers of monocrystalline material to a desirable substrate.

    상세보기
98. Mori Kazuo,JPX, Method of bonding a III-V group compound semiconductor layer on a silicon substrate.

    상세보기
99. Grupen-Shemansky Melissa E. (Phoenix AZ) Cambou Bertrand F. (Mesa AZ), Method of bonding silicon and III-V semiconductor materials.

    상세보기
100. Nuttall Michael ; Ping Er-Xuan ; Hu Yongjun Jeff, Method of depositing polysilicon, method of fabricating a field effect transistor, method of forming a contact to a substrate, method of forming a capacitor.

     상세보기
101. Meyerson Bernard S. (Yorktown Heights NY), Method of dopant enhancement in an epitaxial silicon layer by using germanium.

     상세보기
102. Fitzgerald, Eugene A.; Gerrish, Nicole, Method of fabricating CMOS inverter and integrated circuits utilizing strained silicon surface channel MOSFETs.

     상세보기
103. Gaul Stephen J. (Melbourne FL) Rouse George V. (Indialantic FL), Method of fabricating SOI wafer with SiGe as an etchback film in a BESOI process.

     상세보기
104. Andideh Ebrahim ; Brigham Lawrence ; Chau Robert S. ; Ghani Tahir ; Jan Chia-Hong ; Sandford Justin ; Taylor Mitchell C., Method of fabricating a MOS transistor with a raised source/drain extension.

     상세보기
105. Shideler, Jay Albert; Prasad, Jayasimha Swamy; Schlupp, Ronald Lloyd; Bechdolt, Robert William, Method of fabricating a bipolar transistor using selective epitaxially grown SiGe base layer.

     상세보기
106. Murthy, Anand S.; Chau, Robert S.; Morrow, Patrick; Jan, Chia-Hong; Packan, Paul, Method of fabricating a field effect transistor structure with abrupt source/drain junctions.

     상세보기
107. Fitzgerald, Eugene A., Method of fabricating a relaxed silicon germanium platform having planarizing for high speed CMOS electronics and high speed analog circuits.

     상세보기
108. Suguro Kyoichi (Yokohama JPX), Method of fabricating a semiconductor device having silicided source/drain regions.

     상세보기
109. Gardner Mark I. ; Fulford H. Jim ; Wristers Derick J., Method of fabricating a transistor with a dielectric underlayer and device incorporating same.

     상세보기
110. Mohammad S. Noor (Hopewell Junction NY), Method of fabricating a triple heterojunction bipolar transistor.

     상세보기
111. Dennard Robert H. (Peekskill NY) Meyerson Bernard S. (Yorktown Heights NY) Rosenberg Robert (Peekskill NY), Method of fabricating defect-free silicon on an insulating substrate.

     상세보기
112. Lynch William T. (Apex NC) Wang Kang L. (Santa Monica CA) Tanner Martin O. (Duarte CA), Method of fabricating quantum bridges by selective etching of superlattice structures.

     상세보기
113. Fiorini Paolo,BEX ; Sedky Sherif,EGX ; Caymax Matty,BEX ; Baert Christiaan,BEX, Method of fabrication of an infrared radiation detector and infrared detector device.

     상세보기
114. Bin Yu ; William G. En ; Judy Xilin An ; Concetta E. Riccobene, Method of fabrication of semiconductor-on-insulator (SOI) wafer having a Si/SiGe/Si active layer.

     상세보기
115. Chu, Jack O.; Huang, Feng-Yi; Koester, Steven J.; Sadana, Devendra K., Method of forming a SiGe-on-insulator substrate using separation by implantation of oxygen.

     상세보기
116. Wieczorek Karsten,DEX ; Raab Michael,DEX ; Stephan Rolf,DEX, Method of forming a transistor having a low-resistance gate electrode.

     상세보기
117. Yee-Chia Yeo ; Fu-Liang Yang TW; Chenming Hu TW, Method of forming a transistor with a strained channel.

     상세보기
118. Tejwani Manu J. (Yorktown Heights NY) Iyer Subramanian S. (Yorktown Heights NY), Method of forming an ultra-uniform silicon-on-insulator layer.

     상세보기
119. Gardner Mark I. ; Nguyen Thien T., Method of forming an ultrathin gate dielectric.

     상세보기
120. Abernathey John R. (Essex VT) Cronin John E. (Milton VT) Lasky Jerome B. (Essex Junction VT), Method of forming metal-strapped polysilicon gate electrode for FET device.

     상세보기
121. Noguchi, Takashi; Soneda, Mitsuo, Method of forming n-and p- channel field effect transistors on the same silicon layer having a strain effect.

     상세보기
122. Zdebel Peter J. (Mesa AZ) Vasquez Barbara (Chandler AZ) Liaw Hang M. (Scottsdale AZ) Seelbach Christian A. (Scottsdale AZ), Method of forming planar isolation regions.

     상세보기
123. Ohori Tatsuya (Kawasaki JPX), Method of growing compound semiconductor.

     상세보기
124. Dutartre Didier,FRX, Method of implementation of MOS transistor gates with a high content.

     상세보기
125. Doyle Brian S. ; Roberds Brian ; Lee Jin, Method of increasing the mobility of MOS transistors by use of localized stress regions.

     상세보기
126. Takasaki Kanetake (Kawasaki JPX), Method of making a compound semiconductor crystal-on-substrate structure.

     상세보기
127. Curran Patrick A. (Plano TX), Method of making a heterojunction bipolar transistor with SIPOS.

     상세보기
128. Murthy, Anand S.; Boyanov, Boyan; Soman, Ravindra; Chau, Robert S., Method of making a semiconductor transistor.

     상세보기
129. Brigham Lawrence N. ; Cotner Raymond E. ; Hussein Makarem A., Method of making a transistor having a deposited dual-layer spacer structure.

     상세보기
130. Gardner Mark I. ; Fulford H. Jim ; Wristers Derick J., Method of making disposable channel masking for both source/drain and LDD implant and subsequent gate fabrication.

     상세보기
131. Cronin John E. (Milton VT) Kaanta Carter W. (Colchester VT) Mann Randy W. (Jericho VT) Meulemans Darrell (Jericho VT) Starkey Gordon S. (Essex Junction VT), Method of making overpass mask/insulator for local interconnects.

     상세보기
132. Tseng Horng-Huei,TWX, Method of making titanium silicide source/drains and tungsten silicide gate electrodes for field effect transistors.

     상세보기
133. Nobuyoshi Hattori JP; Satoshi Yamakawa JP; Junji Nakanishi JP, Method of manufacturing SOI substrate and semiconductor device.

     상세보기
134. Naruse Hiroshi (Yokohama JPX), Method of manufacturing a bonded semiconductor substrate and a dielectric isolated bipolar transistor.

     상세보기
135. Cheong, Woo Seock, Method of manufacturing a contact plug for a semiconductor device.

     상세보기
136. Cheong, Woo Seock; Roh, Eui Beom, Method of manufacturing a contact plug in a semiconductor device using selective epitaxial growth of silicon process.

     상세보기
137. In Haeng Lee KR, Method of manufacturing a semiconductor device.

     상세보기
138. Jung Ho Lee KR; Seung Chul Lee KR, Method of manufacturing a semiconductor device.

     상세보기
139. Nagano Takashi,JPX, Method of manufacturing a semiconductor device with a silicide layer.

     상세보기
140. Sugiyama, Naoharu; Kurobe, Atsushi; Tezuka, Tsutomu; Mizuno, Tomohisa; Takagi, Shinichi, Method of manufacturing a substrate using an SiGe layer.

     상세보기
141. Fushida Atsuo,JPX ; Goto Kenichi,JPX ; Yamazaki Tatsuya,JPX ; Sukegawa Takae,JPX ; Kase Masataka,JPX ; Sakuma Takashi,JPX ; Okazaki Keisuke,JPX ; Ota Yuzuru,JPX ; Takagi Hideo,JPX, Method of manufacturing semiconductor device.

     상세보기
142. Nagaoka, Kojiro; Saito, Masaki, Method of manufacturing semiconductor device.

     상세보기
143. Nakajima,Takashi; Miura,Hideo; Ohta,Hiroyuki; Okamoto,Noriaki, Method of manufacturing semiconductor device having conductive thin films.

     상세보기
144. Jung Ho Lee KR, Method of manufacturing transistor having elevated source and drain regions.

     상세보기
145. Godbey David J. (Burtonsville MD), Method of producing a silicon membrane using a silicon alloy etch stop layer.

     상세보기
146. Godbey David J. (Bethesda MD) Hughes Harold L. (West River MD) Kub Francis J. (Severna Park MD), Method of producing a thin silicon-on-insulator layer.

     상세보기
147. Fujioka Hiroshi (Tokyo JPX), Method of producing heterojunction bipolar transistor having narrow band gap base type.

     상세보기
148. Taylor, Jr., William J.; Orlowski, Marius; Gilmer, David C.; Alluri, Prasad V.; Hobbs, Christopher C.; Rendon, Michael J.; Clejan, Iuval R., Method of recrystallizing an amorphous region of a semiconductor.

     상세보기
149. Krishna Vepa (St. Charles MO) Wisnieski Michael S. (O\Fallon MO) Illig Lois (Troy MO), Method of rough polishing semiconductor wafers to reduce surface roughness.

     상세보기
150. Kern Rim, Method to fabricate a strained Si CMOS structure using selective epitaxial deposition of Si after device isolation formation.

     상세보기
151. Chang Chun-Yen,TWX ; Lei Tan-Fu,TWX ; Lin Hsiao-Yi,TWX ; Cheng Juing-Yi,TWX, Method to fabricate the thin film transistor.

     상세보기
152. Yang Hong ; Yu Xing,SGX ; Leung Ying Keung,HKX, Method to form CoSi.sub.2 on shallow junction by Si implantation.

     상세보기
153. Chang Tzong-Sheng,TWX ; Tsai Hung-Chi,TWX ; Tien Bor-Zen,TWX, Method to improve TiSix salicide formation.

     상세보기
154. Plumton Donald L. (Dallas TX) Morris Francis J. (Plano TX) Yang Jau-Yuann (Richardson TX), Method to integrate HBTs and FETs.

     상세보기
155. Liu, Kaiping, Method to produce localized halo for MOS transistor.

     상세보기
156. Song, Won-sang; Park, Jung-woo; Lee, Gil-gwang; Choe, Tae-hee, Methods for fabricating field effect transistors having elevated source/drain regions.

     상세보기
157. Langdo, Thomas A.; Lochtefeld, Anthony J., Methods of fabricating semiconductor structures having epitaxially grown source and drain elements.

     상세보기
158. Gehrke Thomas ; Linthicum Kevin J. ; Davis Robert F., Methods of forming a plurality of semiconductor layers using spaced trench arrays.

     상세보기
159. Zhang, Zhibo; Misra, Veena; Bedair, Salah M. A.; Ozturk, Mehmet, Methods of forming nano-scale electronic and optoelectronic devices using non-photolithographically defined nano-channel templates.

     상세보기
160. Gunn, III, Lawrence C.; Capellini, Giovanni; Rattier, Maxime Jean; Pinguet, Thierry J., Methods of incorporating germanium within CMOS process.

     상세보기
161. Dmbkes Heinrich (Ulm DEX) Herzog Hans-J. (Neu-Ulm DEX) Jorke Helmut (Gerstetten DEX), Modulation doped field effect transistor with doped SixGe₁-x-intrinsic Si layering.

     상세보기
162. Maa, Jer-Shen; Tweet, Douglas J.; Hsu, Sheng Teng; Lee, Jong-Jan, Molecular hydrogen implantation method for forming a relaxed silicon germanium layer with high germanium content.

     상세보기
163. Fattaruso John W., Monolithic inductor with guard rings.

     상세보기
164. Paton, Eric N.; Xiang, Qi; Besser, Paul R.; Lin, Ming-Ren; Ngo, Minh V.; Wang, Haihong, Mosfets incorporating nickel germanosilicided gate and methods for their formation.

     상세보기
165. Oda, Katsuya; Washio, Katsuyoshi, Multi-layered, single crystal field effect transistor.

     상세보기
166. Arimilli, Ravi Kumar; Fields, Jr., James Stephen; Guthrie, Guy Lynn; Joyner, Jody Bern; Lewis, Jerry Don, Multiprocessor system bus protocol with group addresses, responses, and priorities.

     상세보기
167. Kadosh, Daniel; Wristers, Derick J.; Xiang, Qi; Yu, Bin, Narrow width CMOS devices fabricated on strained lattice semiconductor substrates with maximized NMOS and PMOS drive currents.

     상세보기
168. Yuhzoh Tsuda JP; Takayuki Yuasa JP, Nitride semiconductor structure, method for producing a nitride semiconductor structure, and light emitting device.

     상세보기
169. Otto Joachim (Unterschleisseheim DEX), Non-volatile memory cell.

     상세보기
170. Howe Roger T. ; Franke Andrea ; King Tsu-Jae, Polycrystalline silicon germanium films for forming micro-electromechanical systems.

     상세보기
171. Kim Bumman (Richardson TX) Tserng Hua Q. (Dallas TX), Power MISFET.

     상세보기
172. Henley Francois J. ; Cheung Nathan W., Pre-semiconductor process implant and post-process film separation.

     상세보기
173. Canaperi, Donald F.; Chu, Jack Oon; D'Emic, Christopher P.; Huang, Lijuan; Ott, John Albrecht; Wong, Hon-Sum Philip, Preparation of strained Si/SiGe on insulator by hydrogen induced layer transfer technique.

     상세보기
174. Levine Barry Franklin ; Pinzone Christopher James, Process for bonding crystalline substrates with different crystal lattices.

     상세보기
175. Pfiester James R. (Austin TX), Process for fabricating a silicon on insulator field effect transistor.

     상세보기
176. Hartswick Thomas J. (Underhill VT) Kaanta Carter W. (Colchester VT) Lee Pei-Ing P. (Williston VT) Wright Terrance M. (Williston VT), Process for forming refractory metal silicide layers of different thicknesses in an integrated circuit.

     상세보기
177. Prabhakar Venkatraman, Process for forming silicon on insulator devices having elevated source and drain regions.

     상세보기
178. Alexander Yuri Usenko, Process for lift-off of a layer from a substrate.

     상세보기
179. Bensahel Daniel,FRX ; Campidelli Yves,FRX ; Hernandez Caroline,FRX ; Rivoire Maurice,FRX, Process for obtaining a layer of single-crystal germanium or silicon on a substrate of single-crystal silicon or germanium, respectively.

     상세보기
180. Richard Alden DeFelice ; Judith Prybyla, Process for planarization a semiconductor substrate.

     상세보기
181. Kondo Shigeki (Hiratsuka JPX) Matsumoto Shigeyuki (Atsugi JPX) Ishizaki Akira (Atsugi JPX) Inoue Shunsuke (Yokohama JPX) Nakamura Yoshio (Atsugi JPX), Process for preparing semiconductor substrate by bonding to a metallic surface.

     상세보기
182. Cheng, Zhi-Yuan; Fitzgerald, Eugene A.; Antoniadis, Dimitri A.; Hoyt, Judy L., Process for producing semiconductor article using graded epitaxial growth.

     상세보기
183. Cheng, Zhi-Yuan; Fitzgerald, Eugene A.; Antoniadis, Dimitri A.; Hoyt, Judy L., Process for producing semiconductor article using graded epitaxial growth.

     상세보기
184. Ruehrwein Robert A. (67 Hilton Ave. Garden City NY 11530), Process for production of III-V compound crystals.

     상세보기
185. Regolini Jorge,FRX ; Bensahel Daniel,FRX, Process for selectively depositing a refractory metal silicide on silicon, and silicon wafer metallized using this proc.

     상세보기
186. Bruel Michel (Veurey FRX), Process for the production of thin semiconductor material films.

     상세보기
187. Ek Bruce A. ; Iyer Subramanian Srikanteswara ; Pitner Philip Michael ; Powell Adrian R. ; Tejwani Manu Jamndas, Production of substrate for tensilely strained semiconductor.

     상세보기
188. Braithwaite, Glyn; Hammond, Richard; Currie, Matthew, RF circuits including transistors having strained material layers.

     상세보기
189. Currie,Matthew T.; Hammond,Richard, Reacted conductive gate electrodes.

     상세보기
190. Wanlass Mark (Golden CO), Reactor design for uniform chemical vapor deposition-grown films without substrate rotation.

     상세보기
191. Fitzgerald Eugene A. ; Bulsara Mayank T., Relaxed InxGa(1-x)as buffers.

     상세보기
192. Christiansen, Silke H.; Chu, Jack O.; Grill, Alfred; Mooney, Patricia M., Relaxed SiGe layers on Si or silicon-on-insulator substrates by ion implantation and thermal annealing.

     상세보기
193. Christiansen, Silke H.; Chu, Jack O.; Grill, Alfred; Mooney, Patricia M., Relaxed SiGe layers on Si or silicon-on-insulator substrates by ion implantation and thermal annealing.

     상세보기
194. Fitzergald, Eugene A., Relaxed silicon germanium platform for high speed CMOS electronics and high speed analog circuits.

     상세보기
195. Fitzergald, Eugene A., Relaxed silicon germanium platform for high speed CMOS electronics and high speed analog circuits.

     상세보기
196. Fitzergald, Eugene A., Relaxed silicon germanium platform for high speed CMOS electronics and high speed analog circuits.

     상세보기
197. Fitzergald, Eugene A., Relaxed silicon germanium platform for high speed CMOS electronics and high speed analog circuits.

     상세보기
198. Fitzgerald, Eugene A., Relaxed silicon germanium platform for high speed CMOS electronics and high speed analog circuits.

     상세보기
199. Fitzgerald, Eugene A., Relaxed silicon germanium platform for high speed CMOS electronics and high speed analog circuits.

     상세보기
200. Fitzgerald, Eugene A., Relaxed silicon germanium platform for high speed CMOS electronics and high speed analog circuits.

     상세보기
201. Coolbaugh, Douglas Duane; Dupuis, Mark D.; Gallagher, Matthew D.; Geiss, Peter J.; Philips, Brett A., STI pull-down to control SiGe facet growth.

     상세보기
202. Chan Kevin Kok ; Chu Jack Oon ; Ismail Khalid EzzEldin,EGX ; Rishton Stephen Anthony ; Saenger Katherine Lynn, Scalable MOS field effect transistor.

     상세보기
203. Shimizu Hitoshi (Yokohama JPX) Hirayama Yoshiyuki (Yokohama JPX) Irikawa Michinori (Yokohama JPX), Schottky junction device having a Schottky junction of a semiconductor and a metal.

     상세보기
204. Kamins Theodore I. (Palo Alto) Noble David B. (Sunnyvale) Hoyt Judy L. (Palo Alto) Gibbons James F. (Palo Alto) Scott Martin P. (San Francisco CA), Selective and non-selective deposition of Si₁-xGex on a Si subsrate that is partially maske.

     상세보기
205. Liaw Hang M. (Scottsdale AZ) Seelbach Christian A. (Scottsdale AZ), Selective deposition of amorphous and polycrystalline silicon.

     상세보기
206. Ozturk Mehmet C. (Cary NC) Grider Douglas T. (Pleasanton CA) Sanganeria Mahesh K. (Raleigh NC) Ashburn Stanton P. (Cary NC) Wortman Jimmie J. (Chapel Hill NC), Selective deposition of doped silicon-germanium alloy on semiconductor substrate, and resulting structures.

     상세보기
207. Ozturk Mehmet C. (Cary NC) Grider Douglas T. (Raleigh NC) Sanganeria Mahesh K. (Raleigh NC) Ashburn Stanton P. (Cary NC), Selective deposition of doped silion-germanium alloy on semiconductor substrate.

     상세보기
208. Lynch William T. (Summit NJ), Selective epitaxy of silicon in silicon dioxide apertures with suppression of unwanted formation of facets.

     상세보기
209. Lynch William T. (Summit NJ), Selective epitaxy of silicon in silicon dioxide apertures with suppression of unwanted formation of facets.

     상세보기
210. Ozturk Mehmet (Cary NC) Wortman Jimmie (Chapel Hill NC) Grider Douglas (Raleigh NC), Selective germanium deposition on silicon and resulting structures.

     상세보기
211. Ajmera, Atul Champaklal; Cabral, Jr., Cyril; Carruthers, Roy Arthur; Chan, Kevin Kok; Cohen, Guy Moshe; Kozlowski, Paul Michael; Lavoie, Christian; Newbury, Joseph Scott; Roy, Ronnen Andrew, Self-aligned silicide (salicide) process for strained silicon MOSFET ON SiGe and structure formed thereby.

     상세보기
212. Cyril Cabral, Jr. ; Roy Arthur Carruthers ; Kevin K. Chan ; Guy M. Cohen ; Kathryn Wilder Guarini ; James M. Harper ; Christian Lavoie ; Paul M. Solomon, Self-aligned silicide process for reduction of Si consumption in shallow junction and thin SOI electronic devices.

     상세보기
213. Cabral, Jr., Cyril; Chan, Kevin Kok; Cohen, Guy Moshe; Guarini, Kathryn Wilder; Lavoie, Christian; Roy, Ronnen Andrew; Solomon, Paul Michael, Self-aligned silicide process utilizing ion implants for reduced silicon consumption and control of the silicide formation temperature and structure formed thereby.

     상세보기
214. Agnello, Paul D.; Chen, Bomy A.; Crowder, Scott W.; Divakaruni, Ramachandra; Iyer, Subramanian S.; Sinitsky, Dennis, Semiconductor chip having both compact memory and high performance logic.

     상세보기
215. Karl Brunner DE; Karl Eberl DE, Semiconductor components, in particular photodetectors, light emitting diodes, optical modulators and waveguides with multilayer structures grown on silicon substrates.

     상세보기
216. Kobayashi Setsuko,JPX ; Shinohe Takashi,JPX ; Inoue Tomoki,JPX ; Yahata Akihiro,JPX, Semiconductor device.

     상세보기
217. Shinichi Takagi JP, Semiconductor device.

     상세보기
218. Sugiyama, Naoharu; Tezuka, Tsutomu; Mizuno, Tomohisa; Takagi, Shinichi, Semiconductor device.

     상세보기
219. Yuichiro Mitani JP; Ichiro Mizushima JP; Shigeru Kambayashi JP; Hirotaka Nishino ; Masahiro Kashiwagi JP, Semiconductor device and manufacturing method thereof.

     상세보기
220. Sugiyama Naoharu,JPX ; Kurobe Atsushi,JPX, Semiconductor device and memory device.

     상세보기
221. Yuki, Koichiro; Saitoh, Tohru; Kubo, Minoru; Ohnaka, Kiyoshi; Asai, Akira; Katayama, Koji, Semiconductor device and method for fabricating the same.

     상세보기
222. Kasai Naoki,JPX ; Koga Hiroki,JPX, Semiconductor device and method for manufacturing same.

     상세보기
223. Naoharu Sugiyama JP; Atsushi Kurobe JP, Semiconductor device and method for manufacturing the same.

     상세보기
224. Tsutomu Tezuka JP, Semiconductor device and method of manufacturing the same.

     상세보기
225. Usuda, Koji; Takagi, Shinichi, Semiconductor device and method of manufacturing the same.

     상세보기
226. Otani Naoko,JPX ; Katayama Toshiharu,JPX, Semiconductor device comprising trench EEPROM.

     상세보기
227. Murthy Anand ; Jan Chia-Hong ; Andideh Ebrahim ; Weldon Kevin, Semiconductor device having deposited silicon regions and a method of fabrication.

     상세보기
228. Iwamatsu Toshiaki (Hyogo JPX) Inoue Yasuo (Hyogo JPX) Yamaguchi Yasuo (Hyogo JPX) Nishimura Tadashi (Hyogo JPX), Semiconductor device having metal silicide film.

     상세보기
229. Iwamatsu Toshiaki,JPX ; Inoue Yasuo,JPX ; Yamaguchi Yasuo,JPX ; Nishimura Tadashi,JPX, Semiconductor device having metal silicide film and manufacturing method thereof.

     상세보기
230. Wieczorek Karsten,DEX ; Raab Michael,DEX ; Stephan Rolf,DEX, Semiconductor device having metal silicide regions of differing thicknesses above the gate electrode and the source/drain regions, and method of making same.

     상세보기
231. Cheng, Zhiyuan; Fitzgerald, Eugene A.; Antoniadis, Dimitri A., Semiconductor device structure.

     상세보기
232. Takuji Matsumoto JP; Toshiaki Iwamatsu JP; Yuuichi Hirano JP, Semiconductor device, method of manufacturing the same and method of arranging dummy region.

     상세보기
233. Kobayashi Yutaka (Hitachi JPX) Suzuki Takaya (Katsuta JPX), Semiconductor devices and method for making the same.

     상세보기
234. Fitzgerald ; Jr. Eugene A. (Bridgewater NJ), Semiconductor devices with low dislocation defects.

     상세보기
235. Brasen Daniel (Lake Hiawatha NJ) Fitzgerald ; Jr. Eugene A. (Bridgewater NJ) Green Martin L. (New Providence NJ) Monroe Donald P. (Berkeley Heights NJ) Silverman Paul J. (Millburn NJ) Xie Ya-Hong (Fl, Semiconductor heterostructure devices with strained semiconductor layers.

     상세보기
236. Pfiester James R. (Austin TX) Hayden James D. (Austin TX), Semiconductor memory cell.

     상세보기
237. Kauffmann Bruce A. (Jericho VT) Lam Chung H. (Williston VT) Lasky Jerome B. (Essex Junction VT), Semiconductor memory cell and memory array with inversion layer.

     상세보기
238. Christenson John C. (Kokomo IN) Schubert Peter J. (Kokomo IN), Semiconductor mushroom structure fabrication.

     상세보기
239. Nakagawa Kiyokazu (Sayama JPX) Nishida Akio (Misato JPX) Shimada Toshikazu (Kokubunji JPX), Semiconductor optical device, manufacturing method for the same, and opto-electronic integrated circuit using the same.

     상세보기
240. Cheng, Zhi-Yuan; Fitzgerald, Eugene A.; Antoniadis, Dimitri A.; Hoyt, Judy L., Semiconductor substrate structure.

     상세보기
241. Murthy, Anand S.; Doyle, Brian S.; Roberds, Brian E., Semiconductor transistor having a backfilled channel material.

     상세보기
242. Murthy, Anand; Chau, Robert S.; Ghani, Tahir; Mistry, Kaizad R., Semiconductor transistor having a stressed channel.

     상세보기
243. Murthy, Anand; Chau, Robert S.; Ghani, Tahir; Mistry, Kaizad R., Semiconductor transistor having a stressed channel.

     상세보기
244. Murthy, Anand; Chau, Robert S.; Ghani, Tahir; Mistry, Kaizad R., Semiconductor transistor having a stressed channel.

     상세보기
245. Mouli,Chandra, Semiconductor-on-insulator constructions.

     상세보기
246. Chuang K. J.,TWX ; Lui H. S.,TWX, Separated floating gate for EEPROM application.

     상세보기
247. Sugiura Yoshihisa,JPX ; Iwata Yoshihisa,JPX ; Watanabe Hiroshi,JPX, Shielded bit line sensing scheme for nonvolatile semiconductor memory.

     상세보기
248. Kinugawa Masaaki (Tokyo JPX), Short channel CMOS on 110 crystal plane.

     상세보기
249. Schmitz Jurriaan,NLX ; Woerlee Pierre H.,NLX, Si-Ge CMOS semiconductor device.

     상세보기
250. Imai Seiji,JPX ; Hiraoka Yoshiko,JPX ; Kurobe Atsushi,JPX ; Sugiyama Naoharu,JPX ; Tezuka Tsutomu,JPX, Si-SiGe semiconductor device and method of fabricating the same.

     상세보기
251. Ismail Khalid EzzEldin ; Meyerson Bernard S., Si/SiGe vertical junction field effect transistor.

     상세보기
252. Burghartz Joachim N. (Shrub Oak NY) Meyerson Bernard S. (Yorktown Heights NY) Sun Yuan-Chen (Katonah NY), SiGe thin film or SOI MOSFET and method for making the same.

     상세보기
253. Soref Richard A. ; Friedman Lionel R., Silicon-based strain-symmetrized GE-SI quantum lasers.

     상세보기
254. Huang Feng-Yi, Silicon-germanium bicmos on soi.

     상세보기
255. Robinson McDonald ; Westhoff Richard C. ; Hunt Charles E. ; Ling Li, Silicon-germanium-carbon compositions in selective etch processes.

     상세보기
256. Ismail Khalid EzzEldin ; Meyerson Bernard S., Single-transistor logic and CMOS inverters.

     상세보기
257. Bhattacharyya, Arup, Stable PD-SOI devices and methods.

     상세보기
258. Chu Jack Oon ; Ismail Khalid EzzEldin, Strained Si/SiGe layers on insulator.

     상세보기
259. Chu Jack Oon ; Ismail Khalid EzzEldin, Strained Si/SiGe layers on insulator.

     상세보기
260. Wang, Haihong; Xiang, Qi, Strained silicon MOSFET having silicon source/drain regions and method for its fabrication.

     상세보기
261. Djomehri, Ihsan J.; Xiang, Qi; Goo, Jung-Suk; Pan, James N., Strained silicon MOSFETs having NMOS gates with work functions for compensating NMOS threshold voltage shift.

     상세보기
262. Xiang, Qi; Paton, Eric N.; Wang, Haihong, Strained silicon PMOS having silicon germanium source/drain extensions and method for its fabrication.

     상세보기
263. Rim, Kern, Strained silicon on insulator structures.

     상세보기
264. Yeo, Yee-Chia; Yang, Fu-Liang; Hu, Chenming, Strained-channel multiple-gate transistor.

     상세보기
265. Langdo,Thomas A.; Currie,Matthew T.; Hammond,Richard; Lochtefeld,Anthony J.; Fitzgerald,Eugene A., Strained-semiconductor-on-insulator device structures.

     상세보기
266. Lee, Jong-Jan; Hsu, Sheng Teng, Strained-silicon channel CMOS with sacrificial shallow trench isolation oxide liner.

     상세보기
267. Yasutoshi Okuno ; Scott R. Summerfelt, Structure and method for a large-permittivity gate using a germanium layer.

     상세보기
268. Kenji Orita JP; Masahiro Isida JP; Shinji Nakamura JP; Masaaki Yuri JP; Nobuyuki Uemura JP, Substrate containing compound semiconductor, method for manufacturing the same and semiconductor device using the same.

     상세보기
269. Ek Bruce A. (Pelham Manor NY) Iyer Subramanian S. (Yorktown Heights NY) Pitner Philip M. (Wappingers Falls NY) Powell Adrian R. (New Milford CT) Tejwani Manu J. (Yorktown Heights NY), Substrate for tensilely strained semiconductor.

     상세보기
270. Aulicino Anthony M.,CAX ; Lyn Robert J.,CAX, Substrate-holding fixture of non-wettable material.

     상세보기
271. Roberds, Brian; Doyle, Brian S., Technique to obtain high mobility channels in MOS transistors by forming a strain layer on an underside of a channel.

     상세보기
272. Doyle Brian S. ; Roberds Brian ; Lee Jin, Technique to obtain increased channel mobilities in NMOS transistors by gate electrode engineering.

     상세보기
273. Ramaswami Ravi ; Joseph Victor ; Cao Min ; Kamins Theodore I. ; Whitlock John P. ; Prem Anil, Thermal inkjet printhead and high-efficiency polycrystalline silicon resistor system for use therein.

     상세보기
274. Bertin Claude L. (South Burlington VT) DiMaria Donelli J. (Ossining NY) Miyakawa Makoto (Tokyo JPX) Sakaue Yoshinori (Tokyo JPX), Three-dimensional direct-write EEPROM arrays and fabrication methods.

     상세보기
275. Jung Ho Lee KR, Transistor in a semiconductor device and method of manufacturing the same.

     상세보기
276. Murakami Eiichi (Fuchu JPX) Nakagawa Kiyokazu (Sayama JPX) Ohshima Takashi (Fuchu JPX) Eto Hiroyuki (Kokubunji JPX) Miyao Masanobu (Tokorozawa JPX), Transistor provided with strained germanium layer.

     상세보기
277. Chau Robert S. ; Chern Chan-Hong ; Jan Chia-Hong ; Weldon Kevin R. ; Packan Paul A. ; Yau Leopoldo D., Transistor with ultra shallow tip and method of fabrication.

     상세보기
278. Chau Robert S. ; Chern Chan-Hong ; Jan Chia-Hong ; Weldon Kevin R. ; Packan Paul A. ; Yau Leopoldo D., Transistor with ultra shallow tip and method of fabrication.

     상세보기
279. Lin Chih-Hung,TWX ; Lee Robin,TWX, Trench flash memory with nitride spacers for electron trapping.

     상세보기
280. Mohammad S. Noor (Hopewell Junction NY), Triple heterojunction bipolar transistor.

     상세보기
281. Bartelink Dirk J., Vertical CMOS digital multi-valued restoring logic device.

     상세보기
282. Augusto Carlos Jorge Ramiro Proenca,BEX, Vertical MISFET devices.

     상세보기
283. Favors ; Jr. Wesley ; MacDonald Eric William ; Mukherjee Subir ; Warriner Lynn Albert, Voltage controlled oscillator utilizing threshold voltage control of silicon on insulator MOSFETS.

     상세보기
284. Terumoto Akatsuka JP; Keisuke Utsunomiya JP, Voltage controlled oscillator with power amplifier.

     상세보기
285. Fransis Bert L. ; O'Connor John Francis, Wideband, variable gain amplifier.

     상세보기
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