초록 ▼

A circuit and method for correcting for power supply voltage noise using two dummy pixels in each row of pixels of an imager having a number of pixels arranged in rows and columns are described. The dummy pixels are driven by the same power supply as the active pixels but do not have the capability

A circuit and method for correcting for power supply voltage noise using two dummy pixels in each row of pixels of an imager having a number of pixels arranged in rows and columns are described. The dummy pixels are driven by the same power supply as the active pixels but do not have the capability to sense light energy. The first dummy pixel is read at the time the active pixels in a row are reset and stores a signal in a first dummy register related to the voltage level of the power supply at the time the active pixels are reset. The second dummy pixel is read at the time the active pixels in the row are read and stores a signal in a second dummy register related to the voltage level of the power supply at the time the active pixels are read. The signals in the first storage register and second storage register can then be used to correct the signals from the active pixels in the row for the effect of noise caused by power supply voltage level fluctuations.

대표청구항 ▼

What is claimed is: 1. A pixel array, comprising: a number of active pixel circuits arranged in an array of rows and columns of active pixel circuits, wherein each said active pixel circuit has a photo detector and communicates electrically with a power supply; a first dummy pixel circuit for each

What is claimed is: 1. A pixel array, comprising: a number of active pixel circuits arranged in an array of rows and columns of active pixel circuits, wherein each said active pixel circuit has a photo detector and communicates electrically with a power supply; a first dummy pixel circuit for each said row of active pixel circuits, wherein each said first dummy pixel circuit does not have a photo detector and communicates electrically with said power supply; a second dummy pixel circuit for each said row of active pixel circuits wherein each said second dummy pixel circuit does not have a photo detector and communicates electrically with said power supply; a column storage register for each said column of active pixel circuits wherein each said column storage register is connected to all of said active pixel circuits in that said column of active pixel circuits; a first dummy storage register, wherein each of said first dummy pixel circuits are connected to said first dummy storage register; a second dummy storage register, wherein each of said second dummy pixel circuits are connected to said second dummy storage register; a reset line for each of said rows of active pixel circuits wherein one of said reset lines is connected to each said active pixel circuit and said first dummy pixel circuit in each said row of active pixel circuits, and wherein each of said active pixel circuits in a row of said pixel circuits selected for reset is reset and said first dummy pixel in said row of active pixel circuits selected for reset stores a signal in said first dummy storage register related to the value of the voltage of said power supply at the time said active pixel circuits in said row of pixel circuits selected for reset are reset; a row select line for each of said rows of active pixel circuits wherein one of said row select lines is connected to each said active pixel circuit and said second dummy pixel in each said row of active pixel circuits, and wherein each of said active pixel circuits in a row of pixel circuits selected for readout is read and stores a signal in that said column register for the same said column of active pixel circuits and said second dummy pixel in said row of pixel circuits selected for readout stores a signal in said second dummy register related to the value of said voltage of said power supply at the time said active pixel circuits in said row of pixel circuits selected for readout are read; means for determining the difference between said signal stored in said first dummy register and said signal stored in said second dummy register; and means for correcting said signals stored in each of said column storage registers for fluctuations of said voltage of said power supply using said difference between said signal stored in said first dummy register and said signal stored in said second dummy register. 2. The pixel array of claim 1 wherein said photo detector comprises a photodiode and each of said active pixel circuits comprises a first reset transistor and a first row select transistor. 3. The pixel array of claim 2 wherein each of said first reset transistors has a source in electrical communication with said voltage supply. 4. The pixel array of claim 2 wherein each of said first reset transistors in each of said rows of pixel circuits has a gate connected to said reset line for that said row of active pixel circuits. 5. The pixel array of claim 2 wherein each of said first row select transistors has a drain in electrical communication with said column register for that said column of active pixel circuits. 6. The pixel array of claim 2 wherein each of said first row select transistors in each of said rows of pixel circuits has a gate connected to said row select line for that said row of active pixel circuits. 7. The pixel array of claim 1 wherein each of said first dummy pixels comprises a second reset transistor, and wherein each of said second reset transistors in each of said rows of active pixel circuits has a gate connected to said reset line for that said row of active pixel circuits, a source in electrical communication with said power supply, and a drain in electrical communication with said first dummy register. 8. The pixel array of claim 1 wherein each of said second dummy pixels comprises a second row select transistor, and wherein each of said second row select transistors in each of said rows of active pixel circuits has a gate connected to said row select line for that said row of active pixel circuits, a source in electrical communication with said power supply, and a drain in electrical communication with said second dummy register. 9. The pixel array of claim 1 wherein said means for determining the difference between said signal stored in said first dummy register and said signal stored in said second dummy register comprises a subtraction circuit. 10. The pixel array of claim 1 wherein said means for correcting said signals stored in each of said column storage registers for fluctuations of said voltage of said power supply using said difference between said signal stored in said first dummy register and said signal stored in said second dummy register comprises an addition or a subtraction circuit. 11. A method of correcting for noise in a pixel array, comprising: providing a number of active pixel circuits arranged in an array of rows and columns of active pixel circuits, wherein each said active pixel circuit has a photo detector and is supplied by a power supply; providing a first dummy pixel for each row of said active pixel circuits, wherein each said first dummy pixel does not have a photo detector and is supplied by said power supply; providing a second dummy pixel for each row of said active pixel circuits wherein each said second dummy pixel does not have a photo detector and is supplied by said power supply; providing a column storage register for each said column of active pixel circuits wherein each said column storage register is connected to each of said active pixel circuits in that said column of pixel circuits; providing a first dummy storage register wherein said first dummy storage register is connected to each of said first dummy pixels; providing a second dummy storage register wherein said second dummy storage register is connected to each of said second dummy pixels; providing a reset line for each of said rows of active pixel circuits wherein one of said reset lines is connected to each said active pixel circuit and said first dummy pixel circuit in each said row of active pixel circuits, and wherein each of said active pixel circuits in a row of said pixel circuits selected for reset is reset and said first dummy pixel in said row of pixel circuits selected for reset stores a signal in said first dummy storage register related to the value of the voltage of said power supply at the time said active pixel circuits in said row of active pixel circuits selected for reset are reset; providing a row select line for each of said rows of active pixel circuits wherein one of said row select lines is connected to each said active pixel circuit and said second dummy pixel circuit in each said row of active pixel circuits, and wherein each of said active pixel circuits in a row of pixel circuits selected for readout is read and stores a signal in that said column register for the same said column of active pixel circuits and said second dummy pixel in said row of active pixel circuits selected for readout stores a signal in said second dummy register related to the value of said voltage of said power supply at the time said active pixel circuits in said row of pixel circuits selected for readout are read; activating one of said reset lines thereby resetting each of said active pixel circuits in one of said rows of active pixel circuits and storing a signal related to the value of said voltage of said power supply at the time said active pixel circuits in that said row are reset in said first dummy storage register; activating one of said row select lines thereby reading said active pixel circuits in that said row of active pixel circuits, storing a readout signal in said column registers, and storing a signal related to the value of said voltage of said power supply at the time said active pixel circuits in that said row of active pixel circuits are read in said second dummy register; and using the signals stored in said column registers, said first dummy register, and said second dummy register to correct for fluctuations of said voltage of said power supply. 12. The method of claim 11 wherein said photo detector comprises a photodiode and each of said active pixel circuits comprises a first reset transistor and a first row select transistor. 13. The method of claim 12 wherein each of said first reset transistors has a source in electrical communication with said power supply. 14. The method of claim 12 wherein each of said first reset transistors in each of said rows of active pixel circuits has a gate connected to said reset line for that said row of active pixel circuits. 15. The method of claim 12 wherein each of said first row select transistors has a drain in electrical communication with said column register for that said column of pixel circuits. 16. The method of claim 12 wherein each of said first row select transistors in each of said rows of active pixel circuits has a gate connected to said row select line for that said row of active pixel circuits. 17. The method of claim 11 wherein each of said first dummy pixels comprises a second reset transistor, and wherein each of said second reset transistors in each of said rows of active pixel circuits has a gate connected to said reset line for that said row of active pixel circuits, a source in electrical communication with said power supply, and a drain in electrical communication with said first dummy register. 18. The method of claim 11 wherein each of said second dummy pixels comprises a second row select transistor, and wherein each of said second row select transistors in each of said rows of active pixel circuits has a gate connected to said row select line for that said row of active pixel circuits, a source in electrical communication with said power supply, and a drain in electrical communication with said second dummy register. 19. The method of claim 11 further comprising a subtraction circuit for determining the difference between said signal stored in said first dummy register and said signal stored in said second dummy register. 20. The method of claim 11 further comprising an addition or a subtraction circuit for correcting said signals stored in each of said column storage registers for fluctuations of said voltage of said power supply.