IPC분류정보
국가/구분 |
United States(US) Patent
등록
|
국제특허분류(IPC7판) |
|
출원번호 |
US-0254898
(2002-09-24)
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등록번호 |
US-7443757
(2008-10-28)
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발명자
/ 주소 |
- Cernea,Raul Adrian
- Li,Yan
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출원인 / 주소 |
|
대리인 / 주소 |
Davis Wright Tremaine LLP
|
인용정보 |
피인용 횟수 :
7 인용 특허 :
60 |
초록
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A memory device and a method thereof allow sensing a plurality of memory cells in parallel while minimizing errors caused by bit-line to bit-line crosstalk. Essentially, the bit line voltages of the plurality of bit line coupled to the plurality of memory cells are controlled such that the voltage d
A memory device and a method thereof allow sensing a plurality of memory cells in parallel while minimizing errors caused by bit-line to bit-line crosstalk. Essentially, the bit line voltages of the plurality of bit line coupled to the plurality of memory cells are controlled such that the voltage difference between each adjacent pair of lines is substantially independent of time while their conduction currents are being sensed. When this condition is imposed, all the alternate currents due to the various bit line capacitance drop out since they all depend on a time varying voltage difference. In another aspect, sensing the memory cell's conduction current is effected by noting its rate of discharging a dedicated capacitor provided in the sense amplifier.
대표청구항
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It is claimed: 1. A memory device comprising: a plurality of memory cells coupled to a set of bit lines; a plurality of sensing circuits for sensing said plurality of memory cells in parallel, each sensing circuit coupled via a bit line to a memory cell to sense a conduction current therein in orde
It is claimed: 1. A memory device comprising: a plurality of memory cells coupled to a set of bit lines; a plurality of sensing circuits for sensing said plurality of memory cells in parallel, each sensing circuit coupled via a bit line to a memory cell to sense a conduction current therein in order to determined a memory state programmed therein; and a power supply for supplying voltages to said plurality of bit lines such that the voltage difference between each adjacent pair of bit lines thereof is substantially independent of time while their conduction currents are being sensed, thereby creating a substantially zero displacement current condition between adjacent pairs of bit lines so as to prevent current flow between them due to their capacitive coupling. 2. The memory device as in claim 1, wherein said power supply includes a first voltage clamp for clamping each of said plurality of bit lines to a predetermined constant bit line voltage. 3. The memory device as in claim 2, wherein said first voltage clamp includes: a first transistor having a first source and a first drain in series with the bit line to be clamped; and said first transistor having a first gate supplied with a first predetermined gate voltage. 4. The memory device as in claim 3, wherein said first predetermined gate voltage is given by said predetermined constant bit line voltage plus a first threshold voltage of said first transistor. 5. The memory device as in claim 2, further comprising a second voltage clamp for keeping the voltage of said first drain of said first transistor above that of the first source during sensing. 6. The memory device as in claim 5, wherein said second voltage clamp includes: a voltage source; a second transistor having a second source coupled to the first drain of said first transistor and a second drain coupled to said voltage source; and said second transistor having a second gate supplied with a second predetermined gate voltage. 7. The memory device as in claim 6, wherein said second predetermined gate voltage is given by at least said predetermined constant bit line voltage plus said first threshold voltage of said first transistor and a second threshold voltage of said second transistor. 8. In a memory device having a plurality of memory cells being sensed in parallel, a sensing system comprising: a plurality of sensing circuits for sensing said plurality of memory cells in parallel, each sensing circuit coupled via a bit line to a memory cell to sense a conduction current therein in order to determined a memory state programmed therein; and means for maintaining the voltage difference between each adjacent pair of bit lines to be substantially independent of time while their conduction currents are being sensed, thereby creating a substantially zero displacement current condition between adjacent pairs of bit lines so as to prevent current flow between them due to their capacitive coupling. 9. The memory device as in claim 8, wherein said means for maintaining includes means for clamping each of said plurality of bit lines to a predetermined constant bit line voltage during sensing. 10. The memory device as in any one of claims 1-9, wherein said plurality of memory cells is non-volatile memory. 11. The memory device as in any one of claims 1-9, wherein said plurality of memory cells is flash EEPROM. 12. The memory device as in any one of claims 1-9, wherein each memory cell stores one bit of data. 13. The memory device as in any one of claims 1-9, wherein memory cell stores more than one bit of data. 14. The memory device as in claim 1, wherein said each sensing circuit further comprises: a capacitor coupled to discharge via said conduction current; and a voltage comparator for comparing a voltage developed across said capacitor relative to a predetermined voltage level after a predetermined period of discharge time, thereby determining the magnitude said conduction current as a function of a rate of discharge of said capacitor. 15. The memory device as in claim 14, wherein said each sensing circuit further comprises: a current comparator for comparing said conduction current relative to a predetermined current level. 16. The memory device as in claim 14, wherein said each sensing circuit further comprises: means for comparing said conduction current relative to a predetermined current level. 17. The memory device as in any one of claims 14-16, wherein said plurality of memory cells is non-volatile memory. 18. The memory device as in any one of claims 14-16, wherein said plurality of memory cells is flash EEPROM. 19. The memory device as in any one of claims 14-16, wherein each memory cell stores one bit of data. 20. The memory device as in any one of claims 14-16, wherein each memory cell stores more than one bit of data. 21. In a memory device having a plurality of memory cells being read in parallel by having their conduction currents being sensed through a plurality of bit lines, a method of reducing bit-line-to-bit-line coupling during read, comprising: supplying a bit line voltage to each of the plurality of bit lines; controlling the bit line voltages supplied to the plurality of bit lines such that the voltage difference between each adjacent pair of bit lines thereof is substantially independent of time, thereby creating a substantially zero displacement current condition between adjacent pairs of bit lines so as to prevent current flow between them due to their capacitive coupling; and reading the plurality of memory cells by sensing their conduction currents in parallel. 22. The method as in claim 21, wherein: said step of controlling the bit line voltages includes individual bit lines to a constant voltage. 23. The method as in claim 21, wherein: said sensing includes comparing the sensed conduction current with a reference current. 24. The method as in claim 21, wherein: said sensing includes: providing a dedicated capacitor; discharging said dedicated capacitor with the sensed conduction current; and determining the rate of discharging as a function of a magnitude of the sensed conduction current. 25. The method as in claim 22, wherein: said sensing includes: providing a dedicated capacitor; discharging said dedicated capacitor with the sensed conduction current; and determining the rate of discharging as a function of a magnitude of the sensed conduction current. 26. The method as in claim 23, wherein: said sensing includes: providing a dedicated capacitor; discharging said dedicated capacitor with the sensed conduction current; and determining the rate of discharging as a function of a magnitude of the sensed conduction current. 27. The method as any one of claims 21-26, wherein said plurality of memory cells is non-volatile memory. 28. The method as any one of claims 21-26, wherein said plurality of memory cells is flash EEPROM. 29. The method as any one of claims 21-26, wherein each memory cell stores one bit of data. 30. The method as any one of claims 21-26, wherein each memory cell stores more than one bit of data.
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