A network controller having a multiprotocol bus interface adapter coupled between a communication network and a computer bus, the adapter including a predictive time base generator; and a management bus controller adapted to monitor and manage preselected components coupled with one of the communica
A network controller having a multiprotocol bus interface adapter coupled between a communication network and a computer bus, the adapter including a predictive time base generator; and a management bus controller adapted to monitor and manage preselected components coupled with one of the communication network and the computer bus. The management bus controller is adapted to employ an Alert Standard Format (ASF) specification protocol, a System Management Bus (SMBus) specification protocol, an Intelligent Platform Management Interface (IPMI) specification protocol, a Simple Network Management Protocol (SNMP), or a combination thereof. The network controller also includes a 10/100/1000BASE-T IEEE Std. 802.3-compliant transceiver and media access controller coupled with the communication network; a buffer memory coupled with the MAC, wherein the buffer memory includes one of a packet buffer memory, a frame buffer memory, a queue memory, and a combination thereof; and a transmit CPU and a receive CPU coupled with the multiprotocol bus interface adapter and the management bus controller. The network controller can be a single-chip VLSI device in an 0.18 micron CMOS VLSI implementation.
대표청구항▼
What is claimed is: 1. An alert supervisory bus controller, comprising: at least one processor operably coupled with a plurality of state machines that receive a plurality of inputs, the plurality of state machines effecting a plurality of predefined functions upon respective ones of the plurality
What is claimed is: 1. An alert supervisory bus controller, comprising: at least one processor operably coupled with a plurality of state machines that receive a plurality of inputs, the plurality of state machines effecting a plurality of predefined functions upon respective ones of the plurality of inputs, and producing a plurality of states thereby, the at least one processor disposed to monitor the plurality of states; and a rules checker communicatively coupled with the at least one processor, the rules checker evaluating the plurality of states and identifying an alert supervisory state corresponding to at least one alert supervisory message received via at least one of the plurality of inputs, and the at least one processor producing a predefined alert supervisory output responsive to the identified alert supervisory state. 2. The alert supervisory bus controller of claim 1, wherein the rules checker identifies the alert supervisory state as conforming to one or both of Alert Standard Format specification and/or Intelligent Platform Management Interface specification. 3. The alert supervisory bus controller of claim 2, wherein the at least one processor uses firmware to perform operations complying to one or both of Alert Standard Format specification and/or Intelligent Platform Management Interface specification. 4. The alert supervisory bus controller of claim 3, wherein the rules checker identifies one or both of Address Resolution Protocol (ARP) packets and/or Remote Management and Control Protocol (RMCP) packets. 5. The alert supervisory bus controller of claim 4, wherein the at least one processor uses firmware to process and respond to Address Resolution Protocol (ARP) requests. 6. The alert supervisory bus controller of claim 1, wherein the at least one processor and the rules-checker are adapted to operate in an OS-absent environment. 7. The alert supervisory bus controller of claim 1, wherein the plurality of inputs comprise IP packets routed between a remote monitor and a client. 8. An alert supervisory bus controller, comprising: at least one processor for processing at least one alert standard format (ASF) management packet, the at least one processor coupled to an alert supervisory bus and a computer bus, the at least one processor bidirectionally translating data between an alert supervisory protocol and a network protocol; and a network interface coupled with the at least one processor and bidirectionally communicating the data between the at least one processor and a network implementing the network protocol, wherein the at least one processor receives the at least one ASF management packet from the network via the network interface. 9. The alert supervisory bus controller of claim 8, wherein the alert supervisory bus operably couples with the at least one processor one or both of a sensor and/or a management function controller. 10. The alert supervisory bus controller of claim 8, wherein the at least one processor performs operations complying to one or both of Alert Standard Format specification and/or Intelligent Platform Management Interface specification. 11. The alert supervisory bus controller of claim 8, wherein the at least one processor processes and responds to Address Resolution Protocol (ARP) requests from the network. 12. The alert supervisory bus controller of claim 8, wherein the at least one processor formats messages routed between a remote monitor and a client. 13. The alert supervisory bus controller of claim 8, wherein the at least one processor communicates system capabilities to a remote monitor and a client. 14. The alert supervisory bus controller of claim 8, wherein the at least one processor operates in an OS-absent environment. 15. The alert supervisory bus controller of claim 8, wherein the alert supervisory bus comprises an SMBus. 16. The alert supervisory bus controller of claim 8, comprising a host configuration module coupled with the at least one processor and configuring operational parameters in the at least one processor. 17. The alert supervisory bus controller of claim 8, comprising an alert supervisory simulator coupled with the at least one processor and simulating one or both of a sensor and/or a management function controller. 18. The alert supervisory bus controller of claim 8, wherein the network is a Gigabit Ethernet, and the alert supervisory bus controller is a Gigabit Ethernet alerting network controller. 19. A network controller, comprising: a multiprotocol bus interface adapter coupled between a communication network and a multiprotocol computer bus, the multiprotocol bus interface adapter adapted to facilitate data flow between the communication network and the multiprotocol computer bus; and an alert supervisory bus controller coupled with the multiprotocol bus interface adapter, and adapted to monitor and manage preselected components coupled with one or both of the communication network and/or the multiprotocol computer bus, the alert supervisory bus controller intercepts and analyzes at least a portion of the data flow between the communication network and the multiprotocol computer bus to identify an alert supervisory message, and the alert supervisory bus controller redirects the alert supervisory message to another data path. 20. The network controller of claim 19, wherein: the preselected components comprise a plurality of state machines in the network controller; and the alert supervisory message comprises information associated with the state machines. 21. The network controller of claim 19, wherein the alert supervisory bus controller comprises at least one rule checker that identifies the alert supervisory message. 22. The network controller of claim 19, wherein the another data path is an alert supervisory bus. 23. The network controller of claim 19, wherein the alert supervisory bus controller performs operations complying to one or both of Alert Standard Format specification and/or Intelligent Platform Management Interface specification. 24. The network controller of claim 19, wherein the alert supervisory bus controller intercepts and analyzes one or both of Address Resolution Protocol (ARP) packets and/or Remote Management and Control Protocol (RMCP) packets. 25. The network controller of claim 19, wherein the multiprotocol bus interface adapter and the alert supervisory bus controller are adapted to operate in an OS-absent environment.
연구과제 타임라인
LOADING...
LOADING...
LOADING...
LOADING...
LOADING...
이 특허에 인용된 특허 (18)
Cromer Daryl C. ; Ellison Brandon J. ; Kern Eric Richard ; Ward James Peter, Alert mechanism for service interruption from power loss.
Cromer Daryl Carvis ; Ellison Brandon Jon ; Johnson Robert Duane ; Kern Eric Richard ; Locker Howard ; Springfield Randall Scott, Data processing system and method for permitting a server computer system to remotely modify operation of a client system's network hardware.
Cramer Keith D. (Rochester MN) Keller Frederick H. (Byron MN), Method and apparatus for remote maintenance and error recovery in distributed data processing networks.
Stachura, Thomas L.; Smith, Carey W., Method and apparatus for transmitting and receiving network protocol compliant signal packets over a platform bus.
Sundahl, Bradley Edman; O'Mullan, Sean Michael; Yancey, Gregory Charles; Okin, Kenneth Alan, Method and apparatus for staggered start-up of a predefined, random, or dynamic number of flash memory devices.
※ AI-Helper는 부적절한 답변을 할 수 있습니다.