초록 ▼

The capacity of a single high-speed serial link between programmable logic devices or other integrated circuits may be provided using multiple lower-speed serial links arranged in parallel. Circuitry is provided for synchronizing and deskewing serial data streams from the multiple lower-speed serial

The capacity of a single high-speed serial link between programmable logic devices or other integrated circuits may be provided using multiple lower-speed serial links arranged in parallel. Circuitry is provided for synchronizing and deskewing serial data streams from the multiple lower-speed serial links. At a receiving integrated circuit, a first-in-first-out buffer may be associated with each of the lower-speed serial links. Each first-in-first-out buffer may be used to provide both synchronization functions and channel alignment functions.

대표청구항 ▼

What is claimed is: 1. A method of using a single set of first-in-first-out buffers on an integrated circuit to synchronize and deskew data received from multiple serial data streams, comprising: deskewing the multiple serial data streams by writing data from each of the multiple serial data stream

What is claimed is: 1. A method of using a single set of first-in-first-out buffers on an integrated circuit to synchronize and deskew data received from multiple serial data streams, comprising: deskewing the multiple serial data streams by writing data from each of the multiple serial data streams into a respective one of the first-in-first-out buffers only after an alignment character has been detected in that serial data stream; dynamically partitioning at least a given one of the first-in-first-out buffers into a deskew space and a synchronization space by writing the data from the serial data stream associated with that given first-in-first-out buffer into one or more slots in the given first-in-first-out buffer while all remaining slots in the given first-in-first-out buffer are allocated to the synchronization space; dynamically partitioning the synchronization space between underflow space and overflow space; synchronizing the multiple serial data streams by reading deskewed data from each of the respective first-in-first-out buffers using a common clock; decoding the multiple serial streams with 8B/10B decoder circuitry that receives the synchronized and deskewed versions of the multiple serial data streams from the single set of first-in-first-out buffers, wherein the integrated circuit comprises programmable logic; and providing the synchronized, deskewed, and decoded data from the multiple serial data streams to the programmable logic on the integrated circuit. 2. The method defined in claim 1 wherein each first-in-first-out buffer has an associated write pointer and an associated read pointer, the method further comprising generating overflow and underflow flags with the first-in-first-out buffers based on the location of the write pointers with respect to the read pointers. 3. The method defined in claim 1 wherein each of the first-in-first-out buffers has an associated write pointer and an associated read pointer, the method comprising: writing data from the multiple serial data streams into the first-in-first-out buffers using the write pointers, wherein at least two of the write pointers point to different memory slots during writing; and reading the deskewed data from the first-in-first-out buffers using the read pointers, wherein during a given clock cycle of the common clock, each of the read pointers points to the same memory slot in each of the associated first-in-first-out buffers. 4. The method defined in claim 1 further comprising: using clock and data recovery circuitry to extract a recovered clock and recovered data from each of the multiple serial data streams; and using the recovered clock from each serial data stream to write data into its respective first-in-first-out buffer. 5. A method of using first-in-first-out buffers on an integrated circuit to synchronize and deskew data received from multiple serial data streams, comprising: dynamically partitioning at least a given one of the first-in-first-out buffers into a deskew space and a synchronization space by writing the data from the serial data stream associated with that given first-in-first-out buffer into one or more slots in the given first-in-first-out buffer while all remaining slots in the given first-in-first-out buffer are allocated to the synchronization space; dynamically partitioning the synchronization space between underflow space and overflow space; deskewing and synchronizing the data from the multiple serial data streams using only a single write pointer for each of the serial data streams to write data into the first-in-first-out buffer circuitry and using only a single read pointer for each of the serial data streams to read data from the first-in-first-out buffer circuitry; decoding the multiple serial streams with 8B/10B decoder circuitry that receives the deskewed and synchronized versions of the multiple serial data streams from the first-in-first-out buffers, wherein the integrated circuit comprises programmable logic; and providing the deskewed, synchronized, and decoded data from the multiple serial data streams to the programmable logic on the integrated circuit. 6. The method defined in claim 5 further comprising partitioning the first-in-first-out buffer circuitry into deskew space and synchronization space in accordance with user input. 7. A set of circuits on an integrated circuit for synchronizing and deskewing multiple serial data streams, comprising: a plurality of first-in-first-out buffers, each first-in-first-out buffer being associated with a respective one of the multiple serial data streams; 8B/10B decoder circuitry that receives the synchronized and deskewed versions of the multiple serial data streams from the first-in-first-out buffers, wherein the integrated circuit comprises a programmable logic device; and control circuitry that controls the first-in-first-out buffers so that each first-in-first-out buffer performs both synchronization and deskewing operations on its respective serial data stream, wherein the control circuitry is configured to: dynamically partition at least a given one of the first-in-first-out buffers into a deskew space and a synchronization space by writing the data from the serial data stream associated with that given first-in-first-out buffer into one or more slots in the given first-in-first-out buffer while all remaining slots in the given first-in-first-out buffer are allocated to the synchronization space; and dynamically partition the synchronization space between underflow space and overflow space. 8. The set of circuits defined in claim 7 further comprising a clock and data recovery circuit associated with each serial data stream that produces a recovered clock and recovered data from that data stream, wherein the recovered clock from each serial data stream is used to write the recovered data from that serial data stream into the first-in-first-out buffer associated with that serial data stream. 9. The set of circuits defined in claim 7 wherein each first-in-first-out buffer comprises an input that receives data from its associated serial data stream and comprises an output, and wherein the outputs of the first-in-first-out buffers provide synchronized serial data streams that are deskewed with respect to each other. 10. The set of circuits defined in claim 7 further comprising decoder circuitry, wherein synchronized and deskewed data is provided to the decoder circuitry from the first-in-first-out buffers. 11. A set of circuits in which serial data is communicated over a plurality of serial data links, comprising: a first integrated circuit having: circuitry for generating digital signals; a plurality of serializers for serializing the digital signals and providing a corresponding plurality of serial data streams; and a plurality of corresponding differential output buffers connected to the serializers that transmit the serial data streams; a second integrated circuit having: a plurality of differential input buffers that receive the transmitted serial data streams; a plurality of clock and data recovery circuits, each connected to a respective one of the differential input buffers for receiving a respective one of the serial data streams and for providing corresponding recovered data from the serial data streams and recovered clock signals from the serial data streams; a plurality of word-alignment circuits, each of which receives the recovered data and recovered clock signals from a respective one of the clock and data recovery circuits and that provides a corresponding word-aligned data signal; a plurality of first-in-first-out buffers that receive the recovered clock signals, wherein each of the first-in-first-out buffers receives the word-aligned data signal from a respective one of the word-alignment circuits and provides a corresponding data output signal and wherein the data output signals from the first-in-first-out buffers are synchronized and deskewed versions of the multiple serial data streams; 8B/10B decoder circuitry that receives the synchronized and deskewed versions of the multiple serial data streams from the first-in-first-out buffers, wherein the second integrated circuit comprises a programmable logic device; and control circuitry that controls the first-in-first-out buffers so that each first-in-first-out buffer performs both synchronization and deskewing operations on its respective word-aligned data signal, wherein the control circuitry is configured to: dynamically partition at least a given one of the first-in-first-out buffers into a deskew space and a synchronization space by writing data into one or more slots in the given first-in-first-out buffer while all remaining slots in the given first-in-first-out buffer are allocated to the synchronization space; and dynamically partition the synchronization space between underflow space and overflow space. 12. The set of circuits defined in claim 11 further comprising control circuitry that directs each first-in-first-out buffer to perform both synchronization and deskewing operations using only a single write pointer and a single read pointer.