초록 ▼

A PLD with LAB interconnect lines that span adjacent LABs in the array and that have the ability to interconnect two logic elements in the different LABs. The PLD includes a plurality of LABs arranged in an array and a plurality of inter-LAB lines interconnecting the LABs of the array. Each of the L

A PLD with LAB interconnect lines that span adjacent LABs in the array and that have the ability to interconnect two logic elements in the different LABs. The PLD includes a plurality of LABs arranged in an array and a plurality of inter-LAB lines interconnecting the LABs of the array. Each of the LABs include a predetermined number of logic elements, one or more control signals distributed among the predetermined number of logic elements in the LAB, and LAB lines spanning between logic elements in different LABs in the array. In various embodiments, the LAB lines are arranged in a staggered pattern with a predetermined pitch between the lines. In other embodiments, the control signals of adjacent LABs can overlap, allowing control signals to be routed to the logic elements of adjacent LABs.

대표청구항 ▼

What is claimed is: 1. An apparatus, comprising: a programmable logic device, the programmable logic device including: a plurality of LABs arranged in an array; a plurality of inter-LAB lines interconnecting the LABs of the array, wherein each of the LABs further include: a predetermined number of

What is claimed is: 1. An apparatus, comprising: a programmable logic device, the programmable logic device including: a plurality of LABs arranged in an array; a plurality of inter-LAB lines interconnecting the LABs of the array, wherein each of the LABs further include: a predetermined number of logic elements; one or more control signals distributed among the predetermined number of logic elements in the LAB; and LAB lines spanning between logic elements, wherein the logic elements are in different LABs in the array. 2. The apparatus of claim 1, wherein the LAB lines within each LAB are arranged in a staggered pattern. 3. The apparatus of claim 2, wherein the staggered LAB lines within each LAB have a predetermined pitch with respect to one another. 4. The apparatus of claim 3, wherein the predetermined pitch consists of one of the following: one, two, three, four, five, six, seven, eight, or more than eight logic elements respectively. 5. The apparatus of claim 3, wherein the predetermined pitch is an integral fraction of the number of logic elements in the LAB. 6. The apparatus of claim 5, wherein the predetermined pitch consists of one of the following: one half, one third, one quarter, one eighth, or one sixteenth of the number of logic elements in the LAB. 7. The apparatus of claim 1, wherein the LAB lines are configured to both: (i) programmably inter-connect logic elements in the same LAB; and/or (ii) programmably inter-connect logic elements in different LABs. 8. The apparatus of claim 1, wherein each of the LABs in the array have a boundary, the LAB boundary being defined by the predetermined number of logic elements receiving the one or more control signals that are distributed in the LAB respectively. 9. The apparatus of claim 8, wherein the LAB lines that can connect logic elements in different LABs extend beyond the boundary of the LAB to different LABs in the array respectively. 10. The apparatus of claim 8, further comprising overlapping LABs wherein the boundary between adjacent LABs overlap and the control signals from the overlapping LABs are distributed to overlapping logic elements in the overlapping LABs respectively. 11. The apparatus of claim 1, wherein the one or more control signals consist of one or more of the following LAB control signals: clock signals, clock enable signals, clear signals, or load signals. 12. The apparatus of claim 1, wherein each LAB further comprises a programmable interconnect pattern of programmable elements that programmably connect the logic elements of the LAB to both (i) the LAB lines of the LAB; and (ii) the LAB lines of the different LAB. 13. The apparatus of claim 12, wherein the programmable elements consist of one or more of the following: multiplexers, RAM storage cells, ROM storage cell, or programmable fuses. 14. The apparatus of claim 1, wherein the inter-LAB lines consist of one or more of the following: horizontal inter-LAB lines; vertical inter-LAB lines; or L-shaped inter-LAB lines that travel in both the horizontal and vertical directions. 15. The apparatus of claim 1, further comprising a plurality of multiplexers to route signals from the plurality of inter-LAB lines to the LAB lines for each LAB in the array and vice-versa respectively. 16. An apparatus, comprising: a programmable logic device, the programmable logic device including: a plurality of LABs arranged in an array; a plurality of inter-LAB lines interconnecting the LABs of the array, wherein a first LAB in the array further includes: a first predetermined number of logic elements; first LAB lines that interconnect the first predetermined number of logic elements; and a first control signal generated by a first control signal generator, the first control signal being distributed to: (i) the first predetermined number of logic elements in the first LAB; and (ii) at least one logic element in a second LAB, the second LAB adjacent the first LAB in the array. 17. The apparatus of claim 16, wherein the second LAB further comprises: a second predetermined number of logic elements; second LAB lines to interconnect the second predetermined number of logic elements; and a second control signal generated by a second control signals generator, the second signal being distributed to: (i) the second predetermined number of logic elements in the second LAB; and (ii) one of the first predetermined number of logic elements in the first LAB. 18. The apparatus of claim 16, wherein one or more of the first LAB lines of the first LAB spans to the second LAB. 19. The apparatus of claim 16, wherein the first LAB lines of the first LAB are staggered. 20. The apparatus of claim 19, wherein the LAB lines of the first LAB are staggered by a predetermined pitch; the predetermined pitch including one of the following: (i) one, two, three, four, five, six, seven, eight or more logic elements; or (ii) half, quarter, or a third of the first predetermined number of the logic elements of the first LAB. 21. The apparatus of claim 17, wherein one or more of the second LAB lines of the second LAB span to the first LAB. 22. The apparatus of claim 17, wherein the second LAB lines are staggered. 23. An method, comprising: providing a programmable logic device, the provided programmable logic device including: a plurality of LABs arranged in an array; a plurality of inter-LAB lines interconnecting the LABs of the array, wherein each of the provided LABs further include: a predetermined number of logic elements; one or more control signals distributed among the predetermined number of logic elements in the LAB; and LAB lines that can inter-connect logic elements, wherein the logic elements are in different LABs in the array. 24. The method of claim 23, wherein the provided LAB lines within each LAB are provided in a staggered pattern. 25. The method of claim 24, wherein the provided staggered LAB lines within each LAB have a predetermined pitch with respect to one another. 26. A method comprising: providing a programmable logic device, the provided programmable logic device including: a plurality of LABs arranged in an array; a plurality of inter-LAB lines interconnecting the LABs of the array, wherein a first LAB in the array further includes: a first predetermined number of logic elements; first LAB lines that interconnect the predetermined number of logic elements; and a first control signal generated by a first control signal generator, the first control signal being distributed to: (i) the first predetermined number of logic elements in the first LAB; and (ii) a logic element in a second LAB, the second LAB adjacent the first LAB in the array. 27. The method of claim 26, wherein the provided second LAB further comprises: a second predetermined number of logic elements; second LAB lines to interconnect the second predetermined number of logic elements; and a second control signal generated by a second control signal generator, the second signal being distributed to: (i) the second predetermined number of logic elements in the second LAB; and (ii) one of the first predetermined number of logic elements in the first LAB. 28. The apparatus of claim 1, wherein a first subset of the LAB lines are arranged in a staggered pattern with respect to one another and a second subset of the LAB lines are arranged in a non-staggered pattern with respect to one another. 29. The apparatus of claim 1, wherein the different LABs are adjacent to one another in the array of LABs. 30. The apparatus of claim 1, wherein the different LABs are not adjacent to one another in the array of LABs.