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Three-dimensional multichip module 원문보기

IPC분류정보
국가/구분 United States(US) Patent 등록
국제특허분류(IPC7판)
  • H01L-021/44
  • H01L-021/02
출원번호 US-0920022 (2004-08-17)
등록번호 US-7465608 (2008-12-16)
발명자 / 주소
  • Farrar,Paul A.
출원인 / 주소
  • Micron Technology, Inc.
대리인 / 주소
    Knobbe, Martens, Olson & Bear LLP
인용정보 피인용 횟수 : 18  인용 특허 : 71

초록

A three-dimensional multichip module having a base structure formed by a plurality of chips secured together in a stack and a plurality of exterior chips mounted to the exterior faces of the base structure. The multichip module may incorporate memory chips, processor chips, logic chips, A to D conve

대표청구항

What is claimed is: 1. A method of forming a multichip module, comprising: securing together a plurality of semiconductor chips in a manner so as to form a base structure having an upper exterior surface, a lower exterior surface, and a lateral exterior surface, said lateral exterior surface is com

이 특허에 인용된 특허 (71)

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이 특허를 인용한 특허 (18)

  1. Emma, Philip G., 3-D stacked and aligned processors forming a logical processor with power modes controlled by respective set of configuration parameters.
  2. Emma, Philip G., 3-D stacked and aligned processors forming a logical processor with power modes controlled by respective set of configuration parameters.
  3. Buyuktosunoglu, Alper; Emma, Philip G.; Hartstein, Allan M.; Healy, Michael B.; Kailas, Krishnan Kunjunny, 3-D stacked multiprocessor structure with vertically aligned identical layout operating processors in independent mode or in sharing mode running faster components.
  4. Buyuktosunoglu, Alper; Emma, Philip G.; Hartstein, Allan M.; Healy, Michael B.; Kailas, Krishnan Kunjunny, 3-D stacked multiprocessor structure with vertically aligned identical layout operating processors in independent mode or in sharing mode running faster components.
  5. Buyuktosunoglu, Alper; Emma, Philip G.; Hartstein, Allan M.; Healy, Michael B.; Kailas, Krishnan Kunjunny, 3-D stacked multiprocessor structures and methods for multimodal operation of same.
  6. Buyuktosunoglu, Alper; Emma, Philip G.; Hartstein, Allan M.; Healy, Michael B.; Kailas, Krishnan Kunjunny, 3-D stacked multiprocessor structures and methods for multimodal operation of same.
  7. Buyuktosunoglu, Alper; Emma, Philip G.; Hartstein, Allan M.; Healy, Michael B.; Kailas, Krishnan K., 3-D stacked multiprocessor structures and methods to enable reliable operation of processors at speeds above specified limits.
  8. Buyuktosunoglu, Alper; Emma, Philip G.; Hartstein, Allan M.; Healy, Michael B.; Kailas, Krishnan K., 3-D stacked multiprocessor structures and methods to enable reliable operation of processors at speeds above specified limits.
  9. Suh, Min Suk; Lee, Seung Hyun, Cube semiconductor package composed of a plurality of stacked together and interconnected semiconductor chip modules.
  10. Buyuktosunoglu, Alper; Emma, Philip G.; Hartstein, Allan M.; Healy, Michael B.; Kailas, Krishnan K., Memory architectures having wiring structures that enable different access patterns in multiple dimensions.
  11. Buyuktosunoglu, Alper; Emma, Philip G.; Hartstein, Allan M.; Healy, Michael B.; Kailas, Krishnan K., Memory architectures having wiring structures that enable different access patterns in multiple dimensions.
  12. Malek, Shayan; Ardisana, II, John B.; Shah, Dhaval N., Modules for increasing useable space on circuit boards.
  13. Rather, John D. G.; Auner, Gregory W., Multifaced microdevice system array.
  14. Buyuktosunoglu, Alper; Emma, Philip G.; Hartstein, Allan M.; Healy, Michael B.; Kailas, Krishnan K., Three-dimensional computer processor systems having multiple local power and cooling layers and a global interconnection structure.
  15. Buyuktosunoglu, Alper; Emma, Philip G.; Hartstein, Allan M.; Healy, Michael B.; Kailas, Krishnan K., Three-dimensional processing system having at least one layer with circuitry dedicated to scan testing and system state checkpointing of other system layers.
  16. Buyuktosunoglu, Alper; Emma, Philip G.; Hartstein, Allan M.; Healy, Michael B.; Kailas, Krishnan K., Three-dimensional processing system having at least one layer with circuitry dedicated to scan testing and system state checkpointing of other system layers.
  17. Emma, Philip G.; Hartstein, Allan M.; Healy, Michael B.; Kailas, Krishnan K.; Buyuktosunoglu, Alper, Three-dimensional processing system having independent calibration and statistical collection layer.
  18. Buyuktosunoglu, Alper; Emma, Philip G.; Hartstein, Allan M.; Healy, Michael B.; Kailas, Krishnan K., Three-dimensional processing system having multiple caches that can be partitioned, conjoined, and managed according to more than one set of rules and/or configurations.
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