초록 ▼

The idea of the invention is to coat the free surface of patterned Cu conducting lines in on-chip interconnections (BEOL) wiring by a 1-20 nm thick metal layer prior to deposition of the interlevel dielectric. This coating is sufficiently thin so as to obviate the need for additional planarization b

The idea of the invention is to coat the free surface of patterned Cu conducting lines in on-chip interconnections (BEOL) wiring by a 1-20 nm thick metal layer prior to deposition of the interlevel dielectric. This coating is sufficiently thin so as to obviate the need for additional planarization by polishing, while providing protection against oxidation and surface, or interface, diffusion of Cu which has been identified by the inventors as the leading contributor to metal line failure by electromigration and thermal stress voiding. Also, the metal layer increases the adhesion strength between the Cu and dielectric so as to further increase lifetime and facilitate process yield. The free surface is a direct result of the CMP (chemical mechanical polishing) in a damascene process or in a dry etching process by which Cu wiring is patterned. It is proposed that the metal capping layer be deposited by a selective process onto the Cu to minimize further processing. We have used electroless metal coatings, such as CoWP, CoSnP and Pd, to illustrate significant reliability benefits, although chemical vapor deposition (CVD) of metals or metal forming compounds can be employed.

대표청구항 ▼

What is claimed is: 1. A method for forming conductors with high electromigration resistance comprising forming a layer of dielectric on a substrate, forming at least one trench in said layer of dielectric, forming a metal liner in said trench, forming a conductor selected from the group consisting

What is claimed is: 1. A method for forming conductors with high electromigration resistance comprising forming a layer of dielectric on a substrate, forming at least one trench in said layer of dielectric, forming a metal liner in said trench, forming a conductor selected from the group consisting of copper and copper alloys on said metal liner filling said trench, forming a planarized upper surface of said conductor planar with the upper surface of said layer of dielectric, forming a conductive film over said upper surface of said conductor, said conductive film forming a metal to metal metallurgical bond to provide high electromigration resistance and high resistance to thermal stress voiding, annealing said substrate in one of an inert or reducing atmosphere at a temperature of at least 300�� C. for at least 2 hours whereby excellent adhesion is obtained between said conductor and said conductive film, and wherein said conductive film has a thickness of 1 to 20 nanometers and is at least one member selected from the group consisting of CoWP, CoSnP, CoP, CoB, CoSnB, CoWB, NiB, Pd, In, and W. 2. The method of claim 1 wherein said step of forming a conductive film includes the step of forming said conductive film by electroless deposition whereby said upper surface of said conductor is protected from oxidation and corrosion. 3. The method of claim 2 wherein said electroless deposited film has a thickness in the range of 1 to 10 nanometers. 4. The method of claim 2 wherein said electroless deposition includes first immersing said substrate in a solution of metal ions whereby a layer of nanoparticles of metal are formed on said upper surface of said conductor and second immersing said substrate in an electroless complexed solution of metal ions and hypophosphite ions whereby said conductive film formed comprises a metal-phosphide conductive film on said upper surface of said conductor. 5. The method of claim 4 wherein said conductive film is selected from the group consisting of CoWP, CoSnP, and CoP. 6. The method of claim 2 wherein said electroless deposition includes first immersing said substrate in a solution of metal ions whereby a layer of nanoparticles of metal are formed on the surface of said conductor, and second immersing said substrate in an electroless complexed solution of metal ions and dimethylamino borane whereby said conductive film formed comprises a layer of metal-boron conductive film on said upper surface of said conductor. 7. The method of claim 1 wherein said conductive film has a thickness in the range of 1 to 10 nanometers. 8. The method of claim 1 wherein said conductive film is applied on the surface of said conductor by physical methods selected from the group consisting of: Chemical Vapor Deposition (CVD), Physical Vapor Deposition (PVD), evaporation, sputtering and thermal metal interdiffusion. 9. The method of claim 8 wherein said conductive film is selected from the group consisting of Pd, In, W and mixtures thereof.