Solid state imaging device having transition time relationship for drive signals
원문보기
IPC분류정보
국가/구분
United States(US) Patent
등록
국제특허분류(IPC7판)
H04N-003/14
H04N-005/335
H01L-027/00
출원번호
US-0826038
(2004-04-16)
등록번호
US-7468750
(2008-12-23)
우선권정보
JP-2003-113840(2003-04-18)
발명자
/ 주소
Mabuchi,Keiji
Funatsu,Eiichi
Kasai,Masanori
출원인 / 주소
Sony Corporation
대리인 / 주소
Rockey, Depke & Lyons, LLC
인용정보
피인용 횟수 :
14인용 특허 :
6
초록▼
A CMOS sensor has unit pixels each structured by a light receiving element and three transistors, to prevent against the phenomenon of saturation shading and the reduction of dynamic range. The transition time (fall time), in switching off the voltage on a drain line shared in all pixels, is given l
A CMOS sensor has unit pixels each structured by a light receiving element and three transistors, to prevent against the phenomenon of saturation shading and the reduction of dynamic range. The transition time (fall time), in switching off the voltage on a drain line shared in all pixels, is given longer than the transition time in turning of any of the reset line and the transfer line. For this reason, the transistor constituting a DRN drive buffer is made proper in its W/L ratio. Meanwhile, a control resistance or current source is inserted on a line to the GND, to make proper the operation current during driving. This reduces saturation shading amount. By making a reset transistor in a depression type, the leak current to a floating diffusion is suppressed to broaden the dynamic range.
대표청구항▼
What is claimed is: 1. A solid-state imaging device comprising: unit pixels including: a charge generating section for generating a charge in an amount corresponding to a light received, a charge storing part for storing a charge generated by the charge generating section, a transfer gate section a
What is claimed is: 1. A solid-state imaging device comprising: unit pixels including: a charge generating section for generating a charge in an amount corresponding to a light received, a charge storing part for storing a charge generated by the charge generating section, a transfer gate section arranged between the charge generating section and the charge storing part for transferring the signal charge generated by the charge generating section to the charge storing part, a pixel signal generating section for generating a pixel signal corresponding to the signal charge stored in the charge storing part, and a reset section for resetting a level of the charge storing part; a transfer line connected commonly with other unit pixels and connected to the transfer gate section; a transfer drive buffer for driving the transfer line; a reset line connected commonly with other unit pixels and connected to the reset section; a reset drive buffer for driving the reset line; a drain line connected commonly with other unit pixels and connected to the reset section and the pixel signal generating section; a drain drive buffer for driving the drain line; and a signal line for receiving the pixel signal generated by the pixel signal generating section and connected commonly with other unit pixels; whereby a pixel select operation, for outputting the pixel signal generated by the pixel signal generating section to the signal line, is carried out under potential control at the charge storing part; and wherein an off transition time of a voltage waveform on the drain line when driven by the drain drive buffer, is five times or greater and ten thousand times or smaller relative to an off transition time on any of the signals applied to the reset line when driven by the reset drive buffer and the transfer line when driven by the transfer driven buffer. 2. A solid-state imaging device according to claim 1, wherein the off transition time of the signal applied to the drain line is in a range of 50 to 600 times relative to an off transition time of a signal applied to the reset line or the transfer line. 3. A solid-state imaging device according to claim 1, further comprising a pixel region arranged with the unit pixels in a two-dimensional matrix form, having a display resolution on the pixel region conforming to a VGA rating, wherein the off transition time of a signal applied to the drain line is 10 nanoseconds or greater and 1000 nanoseconds or smaller. 4. A solid-state imaging device according to claim 3, wherein the off transition time of a signal applied to the drain line is 40 nanoseconds or greater and 600 nanoseconds or smaller. 5. A solid-state imaging device according to claim 4, wherein the off transition time of a signal applied to the drain line is 170 nanoseconds or greater. 6. A solid-state imaging device according to claim 1, wherein the off transition time of a signal applied to the drain line is a half of a pixel clock period or greater and an off-period or smaller. 7. A solid-state imaging device according to claim 1, wherein the transfer drive buffer includes a transistor connected at least to the transfer line, the reset drive buffer includes a transistor connected at least to the reset line, and the drain drive buffer includes a transistor connected at least to the drain line, wherein the transistor connected to the drain line has a W/L ratio (W is a gate width, L is a gate length) set in a range of 1/5 times to 1/2500 times greater than any of a W/L ratio of the transistor connected to the transfer line and a W/L ratio of the transistor connected to the reset line. 8. A solid-state imaging device according to claim 7, wherein the transistor connected to the drain line has a W/L ratio set in a range of 1/10 times to 1/500 times greater than any of a W/L ratio of the transistor connected to the transfer line and a W/L ratio of the transistor connected to the reset line. 9. A solid-state imaging device according to claim 1, further comprising a resistance element for limiting a drive current provided between an off-side reference line of the drain drive buffer and a reference power source. 10. A solid-state imaging device according to claim 1, further comprising a current source for regulating a drive current provided between an off-side reference line of the drain drive buffer and a reference power source. 11. A solid-state imaging device comprising: unit pixels including: a charge generating section for generating a signal charge in an amount corresponding to a light received, a charge storing part for storing a charge generated by the charge generating section, a transfer gate section arranged between the charge generating section and the charge storing part for transferring the signal charge generated by the charge generating section, a pixel signal generating section for generating a pixel signal corresponding to the signal charge stored in the charge storing part, and a reset section for resetting the signal charge stored in the charge storing part; a transfer line connected commonly with other unit pixels and connected to the transfer gate section; a transfer drive buffer for driving the transfer line; a reset line connected commonly with other unit pixels and connected to the reset section; a reset drive buffer for driving the reset line; a drain line connected commonly with other unit pixels and connected to the reset section and the pixel signal generating section; a drain drive buffer for driving the drain line; and a signal line for receiving the pixel signal generated by the pixel signal generating section and connected commonly with other unit pixels; wherein outputting the pixel signal generated by the pixel signal generating section to the signal line is carried out under potential control at the charge storing part; and wherein an off transition time, of a voltage waveform applied to the drain line when driven by the drain drive buffer is longer than an off transition time on any of the reset line when driven by the reset drive buffer and the transfer line when driven by the transfer driven buffer. 12. A solid-state imaging device comprising: a solid-state imaging element having unit pixels including: a charge generating section for generating a signal charge in an amount corresponding to a light received, a charge storing part for storing a charge generated by the charge generating section, a transfer gate section arranged between the charge generating section and the charge storing part for transferring the signal charge generated by the charge generating section, a pixel signal generating section for generating a pixel signal corresponding to the signal charge stored in the charge storing part, and a reset section for resetting the signal charge stored in the charge storing part; a transfer line connected commonly with other unit pixels and connected to the transfer gate section; a reset line connected commonly with other unit pixels and connected to the reset section; a drain line connected commonly with other unit pixels and connected to the reset section and the pixel signal generating section; and a signal line for receiving the pixel signal generated by the pixel signal generating section and connected commonly with other unit pixels; whereby a pixel select operation, for outputting the pixel signal generated by the pixel signal generating section to the signal line, is carried out under potential control at the charge storing part; and a waveform shaping section for receiving a drive pulse for driving the drain line and carrying out a waveform shaping such that an off transition time for a voltage waveform applied to the drain line, is longer than an off transition time of a voltage waveform applied to the reset line and the transfer line. 13. A solid-state imaging device according to claim 12, wherein the waveform shaping section carries out a waveform shaping such that an off transition time for a voltage waveform applied to the drain line is five times or greater and ten thousand times or smaller than the off transition time for signals applied to the reset line and the transfer line. 14. A drive control method for a solid-state imaging device comprising: unit pixels including: a charge generating section for generating a signal charge in an amount corresponding to a light received, a charge storing part for storing a charge generated by the charge generating section, a transfer gate section arranged between the charge generating section and the charge storing part for transferring the signal charge generated by the charge signal generating section to the charge storing part, a pixel signal generating section for generating a pixel signal corresponding to the signal charge stored at the charge storing part, and a reset section for resetting the signal charge stored in the charge storing part; a transfer line connected commonly with other unit pixels and connected to the transfer gate section; a reset line connected commonly with other unit pixels and connected to the reset section; a drain line connected commonly with other unit pixels and connected to the reset section and the pixel signal generating section; and a signal line for receiving the pixel signal generated by the pixel signal generating section and connected commonly with other unit pixels; whereby a pixel select operation, for outputting the pixel signal generated by the pixel signal generating section to the signal line, is carried out under potential control at the charge storing part, the drive control method characterized in that: the drain line is driven such that an off transition time applied to the drain line is longer than an off transition time of a waveform applied to any of the reset line and the transfer line. 15. A drive control method according to claim 14, wherein the drain line is driven such that an off transition time of a voltage waveform applied to the drain line is five times or greater and ten thousand times or smaller than the off transition time on both the reset line and the transfer line. 16. A solid-state imaging device comprising: an imaging region arranged with a plurality of pixels; and a circuit region for supplying a drive pulse to the imaging region; the pixel having: a photoelectric converting section for generating a charge corresponding to an amount of incident light, a charge storing part for storing a charge read from the photoelectric converting section, and a reset section for resetting the charge stored at the charge storing part; wherein the transfer gate is connected with a transfer line, the reset section is connected with a reset line, and the charge storing part is connected with a drain line; the circuit region supplying a first pulse to the drain line, a second pulse to the reset line, and a third pulse to the transfer line; the first pulse having a waveform longer in off transition time than a waveform of the second pulse and third pulse.
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이 특허에 인용된 특허 (6)
Pritchard J. Orion ; Merrill Richard B. ; Lyon Richard F., Driven capacitor storage pixel sensor and array.
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