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A method for erasing memory cells in a memory array, the method including applying an erase pulse to bits of a cell ensemble of a memory cell array, and performing an erase verification operation only on a subgroup of the cell ensemble being erased to check if the memory cells threshold voltage (Vt)

A method for erasing memory cells in a memory array, the method including applying an erase pulse to bits of a cell ensemble of a memory cell array, and performing an erase verification operation only on a subgroup of the cell ensemble being erased to check if the memory cells threshold voltage (Vt) has been lowered to an erase verify (EV) voltage level.

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What is claimed is: 1. A method for erasing memory cells in a memory array, the method comprising: applying an erase pulse to bits of a cell ensemble of a memory cell array; and designating the entire cell ensemble as erase verified once an erase verification operation on a subgroup of the cell ens

What is claimed is: 1. A method for erasing memory cells in a memory array, the method comprising: applying an erase pulse to bits of a cell ensemble of a memory cell array; and designating the entire cell ensemble as erase verified once an erase verification operation on a subgroup of the cell ensemble being erased indicates a memory cell threshold voltage (Vt) of each cell in the subgroup has reached an erase verify (EV) voltage level. 2. The method according to claim 1, wherein the entire cell ensemble is verified as being erased only after the subgroup has been verified as being erased. 3. The method according to claim 1, wherein the subgroup is verified as being erased to a level lower than the target EV level, in order to insure that the entire cell ensemble has been erased, even though not all the cells have been verified as such. 4. The method according to claim 1, further comprising minimizing verification time overhead. 5. The method according to claim 1, wherein performing the erase verification operation is done after clustering said subgroup to a subset of word lines to reduce switching overhead. 6. The method according to claim 1, and further comprising increasing a set margin between a read level and the erase verify level. 7. The method according to claim 1, further comprising increasing a set margin between a read level and the erase verify and program verify levels. 8. The method according to claim 1, further comprising applying an erase pulse to a plurality of subgroups of said cell ensemble, but not performing erase verification operations on all of said subgroups. 9. The method according to claim 1, further comprising checking that a number of bits have passed a set level, and producing a high probability that the entire cell ensemble has been passed erase verification, even though only a subgroup of cells have been physically verified as passing erase verification. 10. The method according to claim 9, further including applying extra erase pulses after erase verification has been completed. 11. The method according to claim 9, where the subgroup of the cell ensemble which is erase verified is alternated between all the subgroups comprising the cell ensemble, regularly, periodically or randomly from erase operation to erase operation.