이 특허에 인용된 특허 (37)

1. Ting Benjamin S. (Saratoga CA), Apparatus and method for partitioning resources for interconnections.

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2. Nation,George W.; Delp,Gary S., Architecture and/or method for using input/output affinity region for flexible use of hard macro I/O buffers.

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3. Agrawal Om P. (San Jose CA) Wright Michael J. (Menlo Park CA) Shen Ju (San Jose CA), Array of configurable logic blocks including network means for broadcasting clock signals to different pluralities of lo.

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4. Lee Kuochun ; Cui Ying ; Chen Tsung Yen, Automatic configuration of gate array cells using a standard cell function library.

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5. Raman Srilata ; Guruswamy Mohankumar ; Dulitz Daniel Wesley ; Chiluvuri Venkata K. R. ; Maziasz Robert L., Automatic layout standard cell routing.

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6. Sasaki Paul Takao ; Vora Madhukar ; West Burnell G, FPGA with conductors segmented by active repeaters.

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7. John E. McGowan, Field programmable gate array with mask programmed input and output buffers.

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8. Tse John ; Lee Fung Fung ; Mendel David Wolk, Fitting for incremental compilation of electronic designs.

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9. McKenney,Douglas J; Emerson,Steven Mark, Flexible design for memory use in integrated circuits.

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10. Bruce Pedersen ; Francis B. Heile ; Marwan Adel Khalaf ; David Wolk Mendel, Generation of sub-netlists for use in incremental compilation.

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11. Butts Michael R. (Portland OR) Batcheller Jon A. (Newberg OR), Hardware logic emulation system with memory capability.

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12. Gaynes Michael Anthony ; Emerick Alan James ; Puligandla Viswanadham ; Woychik Charles Gerard ; Zalesinski Jerzy Maria, High density integrated circuit packaging with chip stacking and via interconnections.

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13. Maeda Shohei,JPX, Integrated circuit being capable of transferring signals of different voltage levels between its input and output.

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14. Kaneko, Yoshio; Tomishima, Atsushi, Interchangeable FPGA-gate array.

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15. Philip John Cacharelis, Liquid crystal on silicon (LCOS) display pixel with multiple storage capacitors.

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16. Cox, William D., Logic array devices having complex macro-cell architecture and methods facilitating use of same.

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17. Tanaka, Genichi, MACROBLOCK FOR USE IN LAYOUT DESIGN OF SEMICONDUCTOR INTEGRATED CIRCUIT, STORAGE MEDIUM FOR STORING INTELLECTUAL PROPERTY INCLUDING INFORMATION ON THE MACROBLOCK, AND LAYOUT DESIGN METHOD USING THE M.

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18. Leaver Andrew ; Heile Francis B., Mapping heterogeneous logic elements in a programmable logic device.

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19. Buch Kiran B. (Fremont CA) Law Edwin S. (Saratoga CA) Chu Jakong J. (Santa Clara CA), Mask-programmed integrated circuits having timing and logic compatibility to user-configured logic arrays.

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20. Mendel David Wolk, Method and apparatus for contemporaneously compiling an electronic circuit design by contemporaneously bipartitioning the electronic circuit design using parallel processing.

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21. Fruehling, Terry L.; Helm, Troy L.; Waidner, John, Method and circuit for analysis of the operation of a microcontroller using signature analysis of memory.

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22. Zhao,Joe W.; Li,Xiao Yu; Wang,Feng; Ling,Zhi Min, Method for monitoring and improving integrated circuit fabrication using FPGAs.

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23. Trimberger Stephen M., Method for tolerating defective logic blocks in programmable logic devices.

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24. Park, Jonathan; Chen, Eugen; Saito, Richard; Wright, Adam; Ratchev, Evgueni, Method of creating a mask-programmed logic device from a pre-existing circuit design.

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25. Dahl, Peter, Method of generating the padring layout design using automation.

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26. Anderson James M. (Huntington Beach CA) Coulson Andrew R. (Santa Monica CA) Demaioribus Vincent J. (Scott Valley CA) Nicholas Henry T. (Redondo Beach CA), Method of making adaptive configurable gate array by using a plurality of alignment markers.

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27. Rahut,Anirban; Das,Satyaki; Rahman,Arifur, Methods of routing low-power designs in programmable logic devices having heterogeneous routing architectures.

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28. Collmeyer,Arthur; Szepesi,Thomas; Wong,Dickson; Samuels,Allen, Multi-output power supply design system.

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29. Wingren, Matthew Scott; Nation, George Wayne; Delp, Gary Scott; Byrn, Jonathan William, Placement of configurable input/output buffer structures during design of integrated circuits.

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30. Bansal Jai P., Process to personalize master slice wafers and fabricate high density VLSI components with a single masking step.

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31. Shankar Kapil (Fremont CA) Moran Mark A. (San Jose CA) Davies ; Jr. Thomas J. (Portland OR), Programmable integrated-circuit switch.

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32. Osann, Jr., Robert; Eltoukhy, Shafy; Mukund, Shridhar; Smith, Lyle, Programmable logic array embedded in mask-programmed ASIC.

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33. Wayne Yeung ; Chiakang Sung ; Myron W. Wong ; Khai Nguyen ; Bonnie I. Wang ; Xiaobao Wang ; Joseph Huang ; Im Whan Kim, Programmable logic device input/output circuit configurable as reference voltage input circuit.

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34. Schadt, John A.; Andrews, William B.; Chen, Zheng; Myers, Anthony K.; Rhein, David A.; Ziegenfus, Warren L.; Zhang, Fulong; Ding, Ming Hui; Fenstermaker, Larry R., Programmable logic devices with integrated standard-cell logic blocks.

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35. Zaliznyak Arch ; Menon Suresh Manohar ; Sasaki Paul Takao, Scaleable padframe interface circuit for FPGA yielding improved routability and faster chip layout.

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36. Patel Rakesh H. ; Turner John E., Technique of fabricating integrated circuits having interfaces compatible with different operating voltage conditions.

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37. Patel, Rakesh H.; Turner, John E., Technique of fabricating integrated circuits having interfaces compatible with different operating voltage conditions.

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