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Described are arithmetic circuits divided logically into a product generator and an adder. Multiplexing circuitry logically disposed between the product generator and the adder supports conventional functionality by providing partial products from the product generator to addend terminals of the add

Described are arithmetic circuits divided logically into a product generator and an adder. Multiplexing circuitry logically disposed between the product generator and the adder supports conventional functionality by providing partial products from the product generator to addend terminals of the adder. The multiplexing circuitry can also be controlled to direct a number of external added inputs to the adder. The additional addend inputs can include inputs and outputs cascaded from other arithmetic circuits.

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What is claimed is: 1. An integrated circuit having an arithmetic circuit comprising: a product generator having: a multiplier port for receiving a first operand; a multiplicand port for receiving a second operand; and a product port for providing a product of the first and second operands; multip

What is claimed is: 1. An integrated circuit having an arithmetic circuit comprising: a product generator having: a multiplier port for receiving a first operand; a multiplicand port for receiving a second operand; and a product port for providing a product of the first and second operands; multiplexing circuitry having: a first multiplexer input port connected to the product port for receiving the product; a second multiplexer input port connected to the multiplier port and the multiplicand port for bypassing the product generator to provide a bypass port of the product generator; a third multiplexer input port for receiving a cascade input from another product generator; and a multiplexer output port; and an adder having a first addend port connected to the multiplexer output port, a second addend port, and a sum port; the sum port connected to a fourth multiplexer input port of the multiplexing circuitry; the arithmetic circuit being configured as a comb stage. 2. The integrated circuit of claim 1, wherein the product port is a first partial-product port and the product is a first partial product. 3. The integrated circuit of claim 2, the product generator further comprising a second partial-product port providing a second partial product. 4. The integrated circuit of claim 3, wherein the multiplexing circuitry additionally has a fifth multiplexer input port connected to the second partial-product port. 5. The integrated circuit of claim 1, wherein the bypass port connects to the sum port. 6. The integrated circuit of claim 1, wherein the bypass port connects to a third addend port of the adder. 7. The integrated circuit of claim 1, wherein the bypass port connects to a collection of nodes supplying voltages representative of a logic zero. 8. The integrated circuit of claim 1, wherein the sum port is connected to the multiplexing circuitry. 9. The integrated circuit of claim 1, wherein the multiplexing circuitry includes at least one additional product-generator bypass port. 10. The integrated circuit of claim 1, further comprising a shifter having a shifter input port and a shifter output port connected to the bypass port. 11. The integrated circuit of claim 10, further comprising a second bypass port connected to the shifter input port. 12. The integrated circuit of claim 10, wherein the shifter input port connects to the sum port. 13. The integrated circuit of claim 1, wherein the product port connects to the first multiplexer input port via a register. 14. The integrated circuit of claim 1, wherein the adder is a conditional-sum adder. 15. The integrated circuit of claim 1, wherein the multiplexing circuitry includes a plurality of multiplexers. 16. A method of testing the adder of claim 1, the method comprising applying test signals to the bypass port. 17. The integrated circuit of claim 1, wherein: the multiplexing circuitry has a select port; and the adder has the sum port connected to the second multiplexer input port of at least one DSP slice of a plurality of DSP slices each of which includes a respective one of each of the product generator, the multiplexing circuitry, and the adder. 18. The integrated circuit of claim 17, wherein each said DSP slice further includes a control signal port connected to the select port respectively thereof. 19. The integrated circuit of claim 17, further comprising: a plurality of configurable logic blocks; interconnect circuitry; and configuration memory connected to the DSP slices, the configurable logic blocks, and the interconnect circuitry, the configuration memory storing configuration data defining a configuration of the configurable logic blocks, the interconnect circuitry, and the DSP slices. 20. The integrated circuit of claim 18, wherein at least one of the DSP slices sequentially receives sets of control signals via a control signal port in the configuration. 21. The integrated circuit of claim 17, wherein the product port is a first partial-product port, the product being a first partial product, the product generator further including a second partial-product port and a fourth multiplexer input port connected to the second partial-product port. 22. The integrated circuit of claim 17, wherein the second addend port connects to another multiplexer output port. 23. The integrated circuit of claim 17, wherein the multiplexing circuitry includes a plurality of multiplexers. 24. The of PLD claim 17, further comprising a first operand port, a second operand port, and a third operand port, the first operand port and the second operand port respectively for receiving the first operand and the second operand. 25. The integrated circuit of claim 24, wherein the third operand port connects to the second multiplexer input port. 26. The integrated circuit of claim 24, wherein the second multiplexer input port connects to the sum port via a shifter. 27. The integrated circuit of claim 26, wherein the multiplexing circuitry includes a third multiplexer input port connected to a collection of programmable memory cells. 28. The integrated circuit of claim 26, wherein the multiplexing circuitry includes a third multiplexer input port connected to at least one of the multiplier port and the multiplicand port. 29. The integrated circuit of claim 28, wherein the third multiplexer input port is coupled for receiving a concatenation of the multiplier port and the multiplicand port.