Method of configuring a process to obtain a thin layer with a low density of holes
IPC분류정보
국가/구분
United States(US) Patent
등록
국제특허분류(IPC7판)
H01L-021/302
H01L-021/02
출원번호
US-0328061
(2006-01-10)
등록번호
US-7485545
(2009-02-03)
발명자
/ 주소
Ben Mohamed,Nadia
Neyret,Eric
Delprat,Daniel
출원인 / 주소
S.O.I.Tec Silicon on Insulator Technologies
대리인 / 주소
Winston & Strawn LLP
인용정보
피인용 횟수 :
2인용 특허 :
4
초록▼
A method for configuring a process for treating a semiconductor wafer. A minimum layer thickness of a transferred layer to be provided is determined to obtain a processed layer that has a preselected target thickness and target maximum density of through holes that extend completely therethrough, by
A method for configuring a process for treating a semiconductor wafer. A minimum layer thickness of a transferred layer to be provided is determined to obtain a processed layer that has a preselected target thickness and target maximum density of through holes that extend completely therethrough, by conducting a predetermined finishing sequence of operations that improve the surface quality of the layer. The minimum thickness is determined such that the density of through holes remains below the target maximum density after each operation in the finishing sequence.
대표청구항▼
What is claimed is: 1. A method for configuring a process for treating a semiconductor wafer, the method comprising: selecting a target thickness to be obtained for a processed semiconductor layer of the semiconductor wafer, which semiconductor layer is to be transferred from a donor substrate; sel
What is claimed is: 1. A method for configuring a process for treating a semiconductor wafer, the method comprising: selecting a target thickness to be obtained for a processed semiconductor layer of the semiconductor wafer, which semiconductor layer is to be transferred from a donor substrate; selecting a target maximum density of through holes to extend completely through the processed semiconductor layer; selecting a finishing sequence of operations to be conducted on the semiconductor layer after transfer thereof in order to improve surface quality of the transferred semiconductor layer to provide the processed semiconductor layer wherein the selected finishing sequence includes at least one shallow-hole reducing operation that reduces depth of shallow holes that are present in the transferred layer, which shallow holes extend less than completely through the transferred layer; and determining a minimum layer thickness of the transferred layer to be provided by: providing the donor substrate that comprises the semiconductor layer and a region of weakness that is configured to facilitate detachment of the semiconductor layer from a remainder portion of the donor substrate, which semiconductor layer and remainder portion are disposed on opposite sides of the region of weakness, associating semiconductor layer with a support substrate, and detaching the semiconductor layer at the region of weakness from the remainder portion to transfer the semiconductor layer to the support substrate to provide the semiconductor wafer, such that the transferred semiconductor layer has at least said minimum layer thickness; wherein said minimum thickness is determined such that the density of through holes is below said target maximum density after each operation in the finishing sequence, and such that the target thickness is achieved when the finishing sequence is complete. 2. The method of claim 1, wherein the region of weakness, of the donor substrate that includes the semiconductor layer for which the minimum layer thickness is determined, is provided by implanting atomic species into the donor substrate. 3. The method of claim 2, further comprising selecting an implantation energy between about 15 keV and about 120 keV for implanting the atomic species. 4. The method of claim 3, wherein the selected implantation energy is less than about 80 keV. 5. The method of claim 1, wherein the at least one shallow-hole reducing operation comprises a thermal annealing operation. 6. The method of claim 1, wherein the at least one shallow-hole reducing operation comprises a polishing operation. 7. The method of claim 1, wherein the selected finishing sequence comprises at least one succession of a rapid thermal annealing operation and a sacrificial oxidation operation. 8. The method of claim 7, wherein the rapid thermal annealing operation precedes the sacrificial oxidation operation in said succession. 9. The method of claim 1, wherein the selected finishing sequence comprises at least one succession of operations comprising a first sacrificial oxidation operation, followed by a polishing operation, followed by a second sacrificial oxidation operation. 10. The method of claim 1, wherein the selected finishing sequence comprises at least one succession of operation comprising a first sacrificial oxidation operation, followed by a rapid thermal annealing operation, followed by a polishing operation, followed by a second sacrificial oxidation operation. 11. The method of claim 1, wherein the minimum layer thickness is determined for the transferred layer, which is associated with the support substrate with an insulating layer disposed between the transferred layer and the support substrate to provide a semiconductor-on-insulator wafer. 12. The method of claim 11, wherein the transferred layer is made of silicon, and the insulator layer is made of an oxide, to provide a silicon-on-insulator wafer after the detachment. 13. The method of claim 11, wherein the selected finishing sequence comprises at least two sequential successions of operations, each succession comprising a rapid thermal annealing operation followed by a sacrificial oxidation operation, wherein the target maximum density of through holes about 0.1/cm2. 14. The method of claim 1, further comprising determining a depth in the donor substrate at which the region of weakness is to be provided to obtain the transferred layer having at least said determined minimum thickness. 15. The method of claim 1, further comprising: providing the semiconductor wafer with the transferred layer of at least said determined minimum thickness and having a surface quality; and conducting the selected finishing sequence of operations to obtain the processed layer, which has: the improved surface quality compared to the surface quality of the transferred layer, substantially the target thickness, and substantially the target maximum density of through holes. 16. The method of claim 15, wherein the region of weakness is provided at a depth in the donor substrate that is substantially equal to or greater than the determined minimum thickness. 17. A method for configuring a process for treating a semiconductor wafer, the method comprising determining a minimum layer thickness of a transferred layer associated with a support substrate and having a transferred surface quality to obtain a processed layer that has a preselected target thickness and a target maximum density of through holes that extend completely therethrough by conducting a predetermined finishing sequence of operations to improve the surface quality of the processed layer compared to the transferred surface quality, wherein said minimum thickness is determined such that the density of through holes is below said target maximum density after each operation in the finishing sequence, wherein the semiconductor wafer is a semiconductor-on-insulator wafer; the finishing sequence includes at least one shallow hole reducing operation that reduces depth of shallow holes that are present in the transferred layer, which shallow holes extend less than completely through the transferred layer, and with the method further comprising: providing a donor substrate that comprises the semiconductor layer with a region of weakness that is configured to facilitate detachment of the layer to be transferred from a remainder portion of the donor substrate, which transfer layer and remainder portion are disposed on opposite sides of the region of weakness, associating the transfer layer with a support substrate, and detaching the transfer layer at the region of weakness from the remainder portion to transfer it to the support substrate to provide the processed layer having the preselected target thickness and a target maximum density of through holes semiconductor wafer. 18. A method for configuring a process for treating a semiconductor wafer to reduce the number of through holes in a transferred layer, the method comprising: providing a donor substrate of a semiconductor material a layer of which is to be transferred to a support substrate; determining a thickness of the layer to be transferred wherein the thickness is sufficient to allow a finishing sequence of operations to be conducted while also providing a target maximum density of through holes that extend completely through the layer; transferring the layer to the support substrate by: providing the donor substrate with a region of weakness that is configured to facilitate detachment of the semiconductor layer from a remainder portion of the donor substrate, which semiconductor layer and remainder portion are disposed on opposite sides of the region of weakness, associating semiconductor layer with the support substrate, and detaching the semiconductor layer at the region of weakness from the remainder portion to transfer the semiconductor layer to the support substrate to provide the semiconductor wafer, such that the transferred semiconductor layer has at least the minimum layer thickness; and applying a finishing sequence of operations on the layer after transfer to improve surface quality and to provide a processed semiconductor layer that has a density of through holes that is below the target maximum density after each operation in the finishing sequence; wherein the finishing operation includes at least one shallow-hole reducing operation that reduces depth of shallow holes that are present in the transferred layer, which shallow holes extend less than completely through the transferred layer; and wherein the target thickness is achieved when the finishing sequence is complete.
Barge, Thierry; Ghyselen, Bruno; Iwamatsu, Toshiaki; Naruoka, Hideki; Furihata, Junichiro; Mitani, Kiyoshi, Method for treating substrates for microelectronics and substrates obtained by said method.
※ AI-Helper는 부적절한 답변을 할 수 있습니다.