[특허]Differential arc fault detection

Honeywell International Inc.

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특허 상세정보

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Differential arc fault detection

특허상세정보
국가/구분	United States(US) Patent 등록
국제특허분류(IPC7판)	G01R-031/42 G01R-031/40 H02H-003/00
미국특허분류(USC)	324/536; 324/522; 361/042
출원번호	US-0606076 (2006-11-30)
등록번호	US-7489138 (2009-02-10)
발명자 / 주소	Yu,Wenjiang Liu,Zhenning Ye,Yang
출원인 / 주소	Honeywell International Inc.
대리인 / 주소	Caglar, Esq.,Oral
인용정보	피인용 횟수 : 14 인용 특허 : 17

초록
▼

A method and apparatus detect arc faults. The method and apparatus may digitally detect current and voltage signals at a master node (111) positioned at a first point in a wiring system (131). At a second point in the wiring system (131), a slave node (122) may digitally detect current and voltage signals. An arc fault that develops between the first and second points in the wiring system (131) may be detected by comparing the current signals from the master node (111) and from the slave node (122), and comparing the voltage signals from the master node ...

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We claim: 1. An apparatus for detecting arc faults, said apparatus comprising: a master node for digitally detecting a current signal and a voltage signal at a first point in a wiring system; a slave node for digitally detecting a current signal and a voltage signal at a second point in said wiring system; and a detection unit for detecting an arc fault in said wiring system by comparing said current signals from said master node and from said slave node and comparing said voltage signals from said master node and from said slave node by; monitoring a time variation of said current signal from said master node, monitoring a time variation of said voltage signal from said slave node, calculating a difference between said current signals from said master node and from said slave node, when said time variation of said current signal has an abnormal value, and calculating a difference between said voltage signals from said master node and from said slave node, when said time variation of said voltage signal has an abnormal value. 2. The apparatus for detecting arc faults according to claim 1, wherein said master node and said slave node are synchronized to each other with a timing signal. 3. The apparatus for detecting arc faults according to claim 1, wherein said master node, said slave node, and said detection unit communicate with each other through a wireless communication pathway or through at least one Controller Area Network bus. 4. The apparatus for detecting arc faults according to claim 1, wherein said detection unit is associated with said master node or with said slave node. 5. The apparatus for detecting arc faults according to claim 1, wherein a difference between said current signals from said master node and from said slave node contains arcing content during a parallel arc fault, and a difference between said voltage signals from said master node and from said slave node contains arcing content during a series arc fault. 6. The apparatus for detecting arc faults according to claim 1, wherein a difference between said voltage signals from said master node and from said slave node is not impacted by signals induced into a wire in said wiring system by cross-talk or common source impedance feedback, and a difference between said current signals from said master node and from said slave node is not impacted by signal characteristics of loads connected to said master node or to said slave node. 7. The apparatus for detecting arc faults according to claim 1, wherein said master node is associated with an electrical power distribution center, and said slave node is located at the input terminal of a load. 8. An apparatus for detecting arc faults, said apparatus comprising: a master node for detecting a current signal and a voltage signal at a first point in a wiring system; a slave node for detecting a current signal and a voltage signal at a second point in said wiring system, wherein an arc fault is detected in said wiring system by comparing said current signals from said master node and from said slave node, and comparing said voltage signals from said master node and from said slave node; said master node samples said voltage and current signals at said first point, monitors a time variation of its current signal to capture an abnormal current occurrence and calls for current signal data from said slave node when an abnormal current occurrence is observed; said slave node samples said voltage and current signals at said second point, monitors a time variation of its voltage signal to capture an abnormal voltage occurrence, and informs said master node when an abnormal voltage occurrence is observed: and a communication pathway for data and timing communication between said master node and said slave node. 9. The apparatus for detecting arc faults according to claim 8, wherein said master node and said slave node are synchronized to each other with a timing signal and exchange data via said communication pathway. 10. The apparatus for detecting arc faults according to claim 8, wherein said communication pathway includes a wireless communication pathway or at least one Controller Area Network bus. 11. The apparatus for detecting arc faults according to claim 8, wherein a difference between said current signals from said master node and from said slave node contains arcing content during a parallel arc fault, and a difference between said voltage signals from said master node and from said slave node contains arcing content during a series arc fault. 12. The apparatus for detecting arc faults according to claim 8, wherein an arc fault in said wiring system is detected by calculating a root mean square for a difference between said current signals or between said voltage signals from said master node and from said slave node, and comparing said root mean square with a threshold. 13. The apparatus for detecting arc faults according to claim 8, wherein a difference between said voltage signals from said master node and from said slave node is not impacted by signals induced into a wire in said wiring system by cross-talk or common source impedance feedback, and a difference between said current signals from said master node and from said slave node is not impacted by signal characteristics of loads connected to said master node or to said slave node. 14. The apparatus for detecting arc faults according to claim 8, wherein said master node is associated with an electrical power distribution center, and said slave node is located at the input terminal of a load. 15. A method of detecting arc faults, said method comprising: detecting a current signal and a voltage signal at a first point in a wiring system; detecting a current signal and a voltage signal at a second point in said wiring system; detecting an arc fault in said wiring system by comparing said current signals at said first and second points, and comparing said voltage signals at said first and second points; communicating data and timing information between said first point and said second point; wherein said step of detecting a current signal and a voltage signal at said first point includes sampling said voltage and current signals at said first point, and monitoring a time variation of said current signal at said first point to capture an abnormal current occurrence, wherein said step of detecting a current signal and a voltage signal at said second point includes sampling said voltage and current signals at said second point, and monitoring a time variation of said voltage signal at said second point to capture an abnormal voltage occurrence, and wherein said communication of data and timing information includes calling for current signal data from said second point when an abnormal current occurrence is observed, and calling for voltage signal data from said first point when an abnormal voltage occurrence is observed. 16. The method of detecting arc faults as recited in claim 15, wherein communication data and timing information from a master node at the said first point and a slave node at said second point are synchronized with each other with a timing signal. 17. The method of detecting arc faults as recited in claim 15, wherein a difference between said current signals from said first and second points contains arcing content during a parallel arc fault, and a difference between said voltage signals from said first and second points contains arcing content during a series arc fault.

이 특허에 인용된 특허 (17)

이 특허를 인용한 특허 피인용횟수: 14

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Differential arc fault detection

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Differential arc fault detection

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