|국가/구분||United States(US) Patent 등록|
|국제특허분류(IPC7판)||G06F-015/16 G06F-015/76 H03K-017/18 H04K-001/00 H04L-009/00|
|미국특허분류(USC)||380/028; 712/015; 712/029; 712/037; 716/016|
|발명자 / 주소|
|출원인 / 주소|
|대리인 / 주소||
|인용정보||피인용 횟수 : 7 인용 특허 : 380|
An integrated circuit for implementing the secure hash algorithm is provided. According to one aspect of the integrated circuit, the integrated circuit includes a data path and a controller controlling operation of the data path. According to another aspect of the integrated circuit, the data path is capable of handling each round of processing reiteratively. The controller further includes an address control module and a finite state machine.
What is claimed is: 1. An integrated circuit for implementing a secure hash algorithm, comprising: a data path configured to process an input message by performing rounds of the secure hash algorithm, the data path comprising hardware components that are reconfigurable; and a controller configured to control operation of the data path in performing the rounds of the secure hash algorithm, the controller comprising hardware components including an address control module and a finite state machine that cooperate with each other to provide control bits and...