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Context switch data prefetching in multithreaded computer 원문보기

IPC분류정보
국가/구분 United States(US) Patent 등록
국제특허분류(IPC7판)
  • G06F-009/46
  • G06F-012/00
  • G06F-009/26
  • G06F-009/30
  • G06F-009/44
출원번호 US-0739738 (2003-12-18)
등록번호 US-7493621 (2009-02-17)
발명자 / 주소
  • Bradford,Jeffrey Powers
  • Kossman,Harold F.
  • Mullins,Timothy John
출원인 / 주소
  • International Business Machines Corporation
대리인 / 주소
    Wood, Herron & Evans
인용정보 피인용 횟수 : 22  인용 특허 : 14

초록

An apparatus, program product and method initiate, in connection with a context switch operation, a prefetch of data likely to be used by a thread prior to resuming execution of that thread. As a result, once it is known that a context switch will be performed to a particular thread, data may be pre

대표청구항

What is claimed is: 1. A method of performing a context switch operation in a multithreaded computer, the method comprising initiating a prefetch of data likely to be used by a thread prior to resuming execution of the thread, wherein the data for which the prefetch is initiated is determined using

이 특허에 인용된 특허 (14)

  1. Scales ; III Hunter Ledbetter ; Diefendorff Keith Everett ; Olsson Brett ; Dubey Pradeep Kumar ; Hochsprung Ronald Ray ; Beavers Bradford Byron ; Burgess Bradley G. ; Snyder Michael Dean ; May Cathy , Data processing system for processing vector data and method therefor.
  2. Snyder Michael Dean, Data processing system having a data prefetch mechanism and method therefor.
  3. Thompson, Carol L.; Zi gler, Michael L.; Huck, Jerome C.; Dwyer, Lawrence D. K. B., Method and apparatus for enabling a compiler to reduce cache misses by performing pre-fetches in the event of context switch.
  4. Cooksey,Robert N.; Jourdan,Stephan J., Method and apparatus for reinforcing a prefetch chain.
  5. Borkenhagen, John Michael; Eickemeyer, Richard James; Flynn, William Thomas; Wottreng, Andrew Henry, Method and apparatus for selecting thread switch events in a multithreaded processor.
  6. Stone Harold S. ; Sakr Majd F. ; Reinhold Mark B., Method for perfetching structured data.
  7. Schneider Bengt-Olaf, Methods and apparatus for managing scratchpad memory in a multiprocessor data processing system.
  8. Baror Gigy, Organization of an integrated cache unit for flexible usage in supporting multiprocessor operations.
  9. Ben-Meir Amos ; Favor John G., Prefetch instruction mechanism for processor.
  10. Kahle, James Allan; Mayfield, Michael John; O'Connell, Francis Patrick; Ray, David Scott; Silha, Edward John; Tendler, Joel M., Software prefetch system and method for predetermining amount of streamed data.
  11. Pickett James K., Start of access instruction configured to indicate an access mode for fetching memory operands in a microprocessor.
  12. Isaac, Roger D.; Alsup, Mitchell, Stride-based prefetch mechanism using a prediction confidence value.
  13. Kimura Yasunori,JPX, Switching multi-context processor and method overcoming pipeline vacancies.
  14. Mayfield, Michael John; O'Connell, Francis Patrick; Ray, David Scott, System and method for prefetching data using a hardware prefetch mechanism.

이 특허를 인용한 특허 (22)

  1. Gabor, Ron; Sheaffer, Gad; Mendelson, Avi; Weiser, Uri C.; Wang, Hong, Acceleration threads on idle OS-visible thread execution units.
  2. Bradbury, Jonathan D.; Busaba, Fadi Y.; Farrell, Mark S.; Gainey, Jr., Charles W.; Greiner, Dan F.; Heller, Lisa Cranton; Kubala, Jeffrey P.; Osisek, Damian L.; Schmidt, Donald W.; Slegel, Timothy J., Address expansion and contraction in a multithreading computer system.
  3. Bradbury, Jonathan D.; Busaba, Fadi Y.; Farrell, Mark S.; Gainey, Jr., Charles W.; Greiner, Dan F.; Heller, Lisa Cranton; Kubala, Jeffrey P.; Osisek, Damian L.; Schmidt, Donald W.; Slegel, Timothy J., Address expansion and contraction in a multithreading computer system.
  4. Ginzburg, Boris; Ronen, Ronny; Weissmann, Eliezer; Vaithianathan, Karthikeyan; Cohen, Ehud, Context switching mechanism for a processing core having a general purpose CPU core and a tightly coupled accelerator.
  5. Ginzburg, Boris; Ronen, Ronny; Weissmann, Eliezer; Vaithianathan, Karthikeyan; Cohen, Ehud, Context switching mechanism for a processor having a general purpose core and a tightly coupled accelerator.
  6. Alsup, Andrew David, Deterministic microcontroller with context manager.
  7. Chen, Hong-Yi; Sutardja, Sehat, Dual thread processor.
  8. Bradbury, Jonathan D.; Busaba, Fadi Y.; Farrell, Mark S.; Gainey, Jr., Charles W.; Greiner, Dan F.; Heller, Lisa Cranton; Jacobi, Christian; Kubala, Jeffrey P.; Osisek, Damian L.; Schmidt, Donald W.; Slegel, Timothy J., Dynamic enablement of multithreading.
  9. Bartik, Jane H.; Bradbury, Jonathan D.; King, Gary M.; Rosa, Daniel V.; Schmidt, Donald W., Hardware counters to track utilization in a multithreading computer system.
  10. Bartik, Jane H.; Bradbury, Jonathan D.; King, Gary M.; Rosa, Daniel V.; Schmidt, Donald W., Hardware counters to track utilization in a multithreading computer system.
  11. Semin, Andrey, Instruction that specifies an application thread performance state.
  12. Bradbury, Jonathan D.; Busaba, Fadi Y.; Farrell, Mark S.; Gainey, Jr., Charles W.; Greiner, Dan F.; Heller, Lisa Cranton; Kubala, Jeffrey P.; Osisek, Damian L.; Schmidt, Donald W.; Slegel, Timothy J., Method for executing a query instruction for idle time accumulation among cores in a multithreading computer system.
  13. Morita, Teruyuki; Koga, Yoshihiro; Nakajima, Kouji, Multi-threaded processor context switching with multi-level cache.
  14. Bradbury, Jonathan D.; Busaba, Fadi Y.; Farrell, Mark S.; Gainey, Jr., Charles W.; Greiner, Dan F.; Heller, Lisa Cranton; Kubala, Jeffrey P.; Osisek, Damian L.; Schmidt, Donald W.; Slegel, Timothy J., Multithreading computer system and program product for executing a query instruction for idle time accumulation among cores.
  15. Snyder, Michael D.; Whisenhunt, Gary L., Polling using reservation mechanism.
  16. Chen, Hong-Yi; Sutardja, Sehat, System for dynamically allocating processing time to multiple threads.
  17. Tran, Thang M.; Schinzler, Michael B., Systems and methods for reducing branch misprediction penalty.
  18. Bradbury, Jonathan D.; Busaba, Fadi Y.; Farrell, Mark S.; Gainey, Jr., Charles W.; Greiner, Dan F.; Heller, Lisa Cranton; Kubala, Jeffrey P.; Osisek, Damian L.; Schmidt, Donald W.; Slegel, Timothy J., Thread context preservation in a multithreading computer system.
  19. Bradbury, Jonathan D.; Busaba, Fadi Y.; Farrell, Mark S.; Gainey, Jr., Charles W.; Greiner, Dan F.; Heller, Lisa Cranton; Kubala, Jeffrey P.; Osisek, Damian L.; Schmidt, Donald W.; Slegel, Timothy J., Thread context preservation in a multithreading computer system.
  20. Bradbury, Jonathan D.; Busaba, Fadi Y.; Farrell, Mark S.; Gainey, Jr., Charles W.; Greiner, Dan F.; Heller, Lisa Cranton; Kubala, Jeffrey P.; Osisek, Damian L.; Schmidt, Donald W.; Slegel, Timothy J., Thread context restoration in a multithreading computer system.
  21. Bradbury, Jonathan D.; Busaba, Fadi Y.; Farrell, Mark S.; Gainey, Jr., Charles W.; Greiner, Dan F.; Heller, Lisa Cranton; Kubala, Jeffrey P.; Osisek, Damian L.; Schmidt, Donald W.; Slegel, Timothy J., Thread context restoration in a multithreading computer system.
  22. Gootherts, Paul; Larson, Douglas V., Time measurement using a context switch count, an offset, and a scale factor, received from the operating system.
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